random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 12:56:00 +01:00
Code Issues Packages Projects Releases Wiki Activity

board: colibri-imx6ull: fix detecting sd card

Browse Source 
Turns out on certain carrier boards (e.g. Iris V2) and under certain
circumstances (e.g. after a software reset) the SD card may have been
left in a strange state which later failed as follows:

Colibri iMX6ULL # mmc dev 0
Card did not respond to voltage select! : -110

Fix this as follows:
- Re-name the signaling voltage rail regulator from vmmc to vqmmc.
- Fix the name of the GPIO property to gpios.
- Specify 4-bit bus width, no write-protect capability and no 1.8
  volt signaling voltage capability.
- Fix the clock vs. command pull-up vs. push-pull configuration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-04-08 12:28:21 +02:00 committed by Stefano Babic
parent 9cec652ec5
commit a398d7d2d4
1 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/dts/imx6ull-colibri.dtsi
View File

@ -41,9 +41,9 @@
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
reg_sd1_vmmc: regulator-sd1-vmmc { reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio"; compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>; pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on; regulator-always-on;
@ -233,12 +233,15 @@
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>; assigned-clock-rates = <0>, <198000000>;
bus-width = <4>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
disable-wp;
no-1-8-v;
pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_sd1_vmmc>; vqmmc-supply = <&reg_sd1_vqmmc>;
status = "okay"; status = "okay";
}; };
@ -473,8 +476,8 @@
pinctrl_usdhc1: usdhc1-grp { pinctrl_usdhc1: usdhc1-grp {
fsl,pins = < fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
@ -484,8 +487,8 @@
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = < fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@ -495,8 +498,8 @@
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = < fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9