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video: Clean up formatting, spelling mistakes in exynos_dp*

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Aesthetic cleanup in drivers/video/exynos_dp*.[ch] files.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
This commit is contained in:
Robert P. J. Day 2015-12-16 11:31:23 -05:00 committed by Anatolij Gustschin
parent 52bc7c7e2b
commit a418f7e850
2 changed files with 21 additions and 21 deletions
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16
drivers/video/exynos_dp.c
View File

@ -207,7 +207,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
return -EINVAL; return -EINVAL;
} }
/*Refer VESA Display Port Stnadard Ver1.1a Page 120 */ /* Refer VESA Display Port Standard Ver1.1a Page 120 */
if (edp_info->dpcd_rev == DP_DPCD_REV_11) { if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
if (buf[DPCD_MAX_LANE_COUNT] & 0x80) if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
@ -270,7 +270,7 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
return ret; return ret;
} }
/* Set link rate and count as you want to establish*/ /* Set link rate and count as you want to establish */
exynos_dp_set_link_bandwidth(edp_info->lane_bw); exynos_dp_set_link_bandwidth(edp_info->lane_bw);
exynos_dp_set_lane_count(edp_info->lane_cnt); exynos_dp_set_lane_count(edp_info->lane_cnt);
@ -322,7 +322,7 @@ static unsigned int exynos_dp_training_pattern_dis(void)
ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
DPCD_TRAINING_PATTERN_DISABLED); DPCD_TRAINING_PATTERN_DISABLED);
if (ret != EXYNOS_DP_SUCCESS) { if (ret != EXYNOS_DP_SUCCESS) {
printf("DP requst_link_traninig_req failed\n"); printf("DP request_link_training_req failed\n");
return -EAGAIN; return -EAGAIN;
} }
@ -412,7 +412,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
unsigned int dpcd_addr; unsigned int dpcd_addr;
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
/*lane_num value is used as arry index, so this range 0 ~ 3 */ /* lane_num value is used as array index, so this range 0 ~ 3 */
dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
@ -433,7 +433,7 @@ static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
ret = exynos_dp_training_pattern_dis(); ret = exynos_dp_training_pattern_dis();
if (ret != EXYNOS_DP_SUCCESS) { if (ret != EXYNOS_DP_SUCCESS) {
printf("DP training_patter_disable() failed\n"); printf("DP training_pattern_disable() failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL; edp_info->lt_info.lt_status = DP_LT_FAIL;
} }
@ -523,7 +523,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
ret = exynos_dp_write_bytes_to_dpcd( ret = exynos_dp_write_bytes_to_dpcd(
DPCD_TRAINING_PATTERN_SET, 5, buf); DPCD_TRAINING_PATTERN_SET, 5, buf);
if (ret != EXYNOS_DP_SUCCESS) { if (ret != EXYNOS_DP_SUCCESS) {
printf("DP write traning pattern1 failed\n"); printf("DP write training pattern1 failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL; edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret; return ret;
} else } else
@ -567,7 +567,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
ret = exynos_dp_write_bytes_to_dpcd( ret = exynos_dp_write_bytes_to_dpcd(
DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
if (ret != EXYNOS_DP_SUCCESS) { if (ret != EXYNOS_DP_SUCCESS) {
printf("DP write traning pattern2 failed\n"); printf("DP write training pattern2 failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL; edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret; return ret;
} }
@ -738,7 +738,7 @@ static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
ret = exynos_dp_sw_link_training(edp_info); ret = exynos_dp_sw_link_training(edp_info);
if (ret != EXYNOS_DP_SUCCESS) if (ret != EXYNOS_DP_SUCCESS)
printf("DP dp_sw_link_traning() failed\n"); printf("DP dp_sw_link_training() failed\n");
return ret; return ret;
} }

26
drivers/video/exynos_dp_lowlevel.c
View File

@ -44,7 +44,7 @@ static void exynos_dp_enable_video_input(unsigned int enable)
reg = readl(&dp_regs->video_ctl1); reg = readl(&dp_regs->video_ctl1);
reg &= ~VIDEO_EN_MASK; reg &= ~VIDEO_EN_MASK;
/* enable video input*/ /* enable video input */
if (enable) if (enable)
reg |= VIDEO_EN_MASK; reg |= VIDEO_EN_MASK;
@ -55,13 +55,13 @@ static void exynos_dp_enable_video_input(unsigned int enable)
void exynos_dp_enable_video_bist(unsigned int enable) void exynos_dp_enable_video_bist(unsigned int enable)
{ {
/*enable video bist*/ /* enable video bist */
unsigned int reg; unsigned int reg;
reg = readl(&dp_regs->video_ctl4); reg = readl(&dp_regs->video_ctl4);
reg &= ~VIDEO_BIST_MASK; reg &= ~VIDEO_BIST_MASK;
/*enable video bist*/ /* enable video bist */
if (enable) if (enable)
reg |= VIDEO_BIST_MASK; reg |= VIDEO_BIST_MASK;
@ -112,7 +112,7 @@ static void exynos_dp_init_analog_param(void)
/* /*
* Set AUX TX terminal resistor to 102 ohm * Set AUX TX terminal resistor to 102 ohm
* Set AUX channel amplitude control * Set AUX channel amplitude control
*/ */
reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
writel(reg, &dp_regs->pll_filter_ctl1); writel(reg, &dp_regs->pll_filter_ctl1);
@ -146,7 +146,7 @@ static void exynos_dp_init_interrupt(void)
*/ */
writel(INT_POL, &dp_regs->int_ctl); writel(INT_POL, &dp_regs->int_ctl);
/* Clear pending regisers */ /* Clear pending registers */
writel(0xff, &dp_regs->common_int_sta1); writel(0xff, &dp_regs->common_int_sta1);
writel(0xff, &dp_regs->common_int_sta2); writel(0xff, &dp_regs->common_int_sta2);
writel(0xff, &dp_regs->common_int_sta3); writel(0xff, &dp_regs->common_int_sta3);
@ -165,7 +165,7 @@ void exynos_dp_reset(void)
{ {
unsigned int reg_func_1; unsigned int reg_func_1;
/*dp tx sw reset*/ /* dp tx sw reset */
writel(RESET_DP_TX, &dp_regs->tx_sw_reset); writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
exynos_dp_enable_video_input(DP_DISABLE); exynos_dp_enable_video_input(DP_DISABLE);
@ -287,7 +287,7 @@ int exynos_dp_init_analog_func(void)
unsigned int retry_cnt = 10; unsigned int retry_cnt = 10;
unsigned int reg; unsigned int reg;
/*Power On All Analog block */ /* Power On All Analog block */
exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
reg = PLL_LOCK_CHG; reg = PLL_LOCK_CHG;
@ -297,14 +297,14 @@ int exynos_dp_init_analog_func(void)
reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
writel(reg, &dp_regs->debug_ctl); writel(reg, &dp_regs->debug_ctl);
/*Assert DP PLL Reset*/ /* Assert DP PLL Reset */
reg = readl(&dp_regs->pll_ctl); reg = readl(&dp_regs->pll_ctl);
reg |= DP_PLL_RESET; reg |= DP_PLL_RESET;
writel(reg, &dp_regs->pll_ctl); writel(reg, &dp_regs->pll_ctl);
mdelay(1); mdelay(1);
/*Deassert DP PLL Reset*/ /* Deassert DP PLL Reset */
reg = readl(&dp_regs->pll_ctl); reg = readl(&dp_regs->pll_ctl);
reg &= ~(DP_PLL_RESET); reg &= ~(DP_PLL_RESET);
writel(reg, &dp_regs->pll_ctl); writel(reg, &dp_regs->pll_ctl);
@ -336,7 +336,7 @@ void exynos_dp_init_hpd(void)
{ {
unsigned int reg; unsigned int reg;
/* Clear interrupts releated to Hot Plug Dectect */ /* Clear interrupts related to Hot Plug Detect */
reg = HOTPLUG_CHG | HPD_LOST | PLUG; reg = HOTPLUG_CHG | HPD_LOST | PLUG;
writel(reg, &dp_regs->common_int_sta4); writel(reg, &dp_regs->common_int_sta4);
@ -366,7 +366,7 @@ void exynos_dp_init_aux(void)
{ {
unsigned int reg; unsigned int reg;
/* Clear inerrupts related to AUX channel */ /* Clear interrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR; reg = RPLY_RECEIV | AUX_ERR;
writel(reg, &dp_regs->int_sta); writel(reg, &dp_regs->int_sta);
@ -377,7 +377,7 @@ void exynos_dp_init_aux(void)
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, &dp_regs->aux_hw_retry_ctl); writel(reg, &dp_regs->aux_hw_retry_ctl);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
reg = DEFER_CTRL_EN | DEFER_COUNT(1); reg = DEFER_CTRL_EN | DEFER_COUNT(1);
writel(reg, &dp_regs->aux_ch_defer_ctl); writel(reg, &dp_regs->aux_ch_defer_ctl);
@ -1040,7 +1040,7 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
writel(reg, &dp_regs->video_ctl10); writel(reg, &dp_regs->video_ctl10);
/*Set video mode to slave mode */ /* Set video mode to slave mode */
reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
writel(reg, &dp_regs->soc_general_ctl); writel(reg, &dp_regs->soc_general_ctl);
} }