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Merge patch series "Add bitbang feature for npcm8xx and driver"

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Michael Chang <zhang971090220@gmail.com> says:

I am resubmitting the patch titled "Add bitbang feature for npcm8xx
and driver" for review and inclusion in the upstream project.

Driver didn't support bitbang feature.
Add bb_miiphy_bus function for driver and open feature for npcm8xx

the log is as below:
-------------------------------------------------
U-Boot 2024.10-g30b9cdaf2df5-dirty (Jan 09 2025 - 00:57:37 +0000)

CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree)
DRAM:  1 GiB
RNG: NPCM RNG module bind OK
OTP: NPCM OTP module bind OK
AES: NPCM AES module bind OK
SHA: NPCM SHA module bind OK
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
Core:  649 devices, 28 uclasses, devicetree: separate
WDT:   Not starting watchdog@901c
MMC:   sdhci@f0842000: 0
Loading Environment from SPIFlash... SF:
Detected w25q512jvq with page size 256 Bytes, erase size 64 KiB,
total 64 MiB
OK
In:    serial@0
Out:   serial@0
Err:   serial@0
Net:   eth0: eth@f0802000, eth1: eth@f0804000, eth3: eth@f0808000
Hit any key to stop autoboot:  0
U-Boot>
U-Boot>
U-Boot>setenv ipaddr 192.168.16.3
U-Boot>ping 192.168.16.12
eth@f0802000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0802000
eth@f0804000 Waiting for PHY auto negotiation to complete
......... TIMEOUT !
Could not initialize PHY eth@f0804000
Speed: 100, full duplex
Using eth@f0808000 device
host 192.168.16.12 is alive

Link: https://lore.kernel.org/r/20250117104540.1580343-1-zhang971090220@gmail.com
This commit is contained in:
Tom Rini 2025-01-23 18:45:56 -06:00
commit a9813506c4
4 changed files with 123 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/nuvoton-npcm845-evb.dts
View File

@ -190,6 +190,7 @@
snps,mdio-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
snps,bitbang-delay = <1>;
snps,reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio93 */
status = "okay";
};

4
configs/arbel_evb_defconfig
View File

@ -80,6 +80,10 @@ CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_NPCM8XX=y
CONFIG_DM_REGULATOR=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=0
CONFIG_DM_REGULATOR_NPCM8XX=y
CONFIG_RNG_NPCM=y
CONFIG_DM_SERIAL=y

113
drivers/net/designware.c
View File

@ -784,6 +784,39 @@ int designware_eth_probe(struct udevice *dev)
priv->bus = miiphy_get_dev_by_name(dev->name);
priv->dev = dev;
#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
if (dev_read_bool(dev, "snps,bitbang-mii")) {
int bus_idx;
debug("\n%s: use bitbang mii..\n", dev->name);
ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
&priv->mdc_gpio, GPIOD_IS_OUT
| GPIOD_IS_OUT_ACTIVE);
if (ret) {
debug("no mdc-gpio\n");
return ret;
}
ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
&priv->mdio_gpio, GPIOD_IS_OUT
| GPIOD_IS_OUT_ACTIVE);
if (ret) {
debug("no mdio-gpio\n");
return ret;
}
priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) {
if (!bb_miiphy_buses[bus_idx].priv) {
bb_miiphy_buses[bus_idx].priv = priv;
strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name,
MDIO_NAME_LEN);
priv->bus->read = bb_miiphy_read;
priv->bus->write = bb_miiphy_write;
break;
}
}
}
#endif
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
if (!ret)
@ -894,3 +927,83 @@ static struct pci_device_id supported[] = {
};
U_BOOT_PCI_DEVICE(eth_designware, supported);
#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct dw_eth_dev *priv = bus->priv;
struct gpio_desc *desc = &priv->mdio_gpio;
desc->flags = 0;
dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
return 0;
}
static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct dw_eth_dev *priv = bus->priv;
struct gpio_desc *desc = &priv->mdio_gpio;
desc->flags = 0;
dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
return 0;
}
static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct dw_eth_dev *priv = bus->priv;
if (v)
dm_gpio_set_value(&priv->mdio_gpio, 1);
else
dm_gpio_set_value(&priv->mdio_gpio, 0);
return 0;
}
static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct dw_eth_dev *priv = bus->priv;
*v = dm_gpio_get_value(&priv->mdio_gpio);
return 0;
}
static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct dw_eth_dev *priv = bus->priv;
if (v)
dm_gpio_set_value(&priv->mdc_gpio, 1);
else
dm_gpio_set_value(&priv->mdc_gpio, 0);
return 0;
}
static int dw_eth_bb_delay(struct bb_miiphy_bus *bus)
{
struct dw_eth_dev *priv = bus->priv;
udelay(priv->bb_delay);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = BB_MII_DEVNAME,
.mdio_active = dw_eth_bb_mdio_active,
.mdio_tristate = dw_eth_bb_mdio_tristate,
.set_mdio = dw_eth_bb_set_mdio,
.get_mdio = dw_eth_bb_get_mdio,
.set_mdc = dw_eth_bb_set_mdc,
.delay = dw_eth_bb_delay,
.priv = NULL,
}
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
#endif

6
drivers/net/designware.h
View File

@ -229,7 +229,11 @@ struct dw_eth_dev {
u32 max_speed;
u32 tx_currdescnum;
u32 rx_currdescnum;
#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
u32 bb_delay;
struct gpio_desc mdc_gpio;
struct gpio_desc mdio_gpio;
#endif
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
#if CONFIG_IS_ENABLED(DM_GPIO)