mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
arm: dts: imx7: sync with Linux
Sync with Linux commit 60cc43fc8884 ("Linux 4.17-rc1").
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This commit is contained in:
Stefan Agner
Stefano Babic
parent
627544506f
commit
aba6a0fb8f
@ -42,6 +42,7 @@
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*/
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#include <dt-bindings/clock/imx7d-clock.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@ -57,7 +58,7 @@
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* Also for U-Boot there must be a pre-existing /memory node.
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*/
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chosen {};
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memory { device_type = "memory"; reg = <0 0>; };
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memory { device_type = "memory"; };
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aliases {
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gpio0 = &gpio1;
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@ -115,11 +116,77 @@
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clock-output-names = "osc";
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};
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usbphynop1: usbphynop1 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX7D_USB_PHY1_CLK>;
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clock-names = "main_clk";
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#phy-cells = <0>;
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};
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usbphynop3: usbphynop3 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
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clock-names = "main_clk";
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#phy-cells = <0>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupt-parent = <&gpc>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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replicator {
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/*
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* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell"
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*/
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compatible = "arm,coresight-replicator";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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interrupt-parent = <&gpc>;
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ranges;
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funnel@30041000 {
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@ -259,62 +326,18 @@
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};
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};
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replicator {
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/*
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* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell"
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*/
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compatible = "arm,coresight-replicator";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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intc: interrupt-controller@31001000 {
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compatible = "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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reg = <0x31001000 0x1000>,
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<0x31002000 0x2000>,
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<0x31004000 0x2000>,
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<0x31006000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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aips1: aips-bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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@ -482,20 +505,49 @@
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status = "disabled";
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};
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kpp: kpp@30320000 {
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compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
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reg = <0x30320000 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_KPP_ROOT_CLK>;
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status = "disabled";
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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};
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gpr: iomuxc-gpr@30340000 {
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compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
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compatible = "fsl,imx7d-iomuxc-gpr",
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"fsl,imx6q-iomuxc-gpr", "syscon";
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reg = <0x30340000 0x10000>;
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};
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ocotp: ocotp-ctrl@30350000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,imx7d-ocotp", "syscon";
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reg = <0x30350000 0x10000>;
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clocks = <&clks IMX7D_OCOTP_CLK>;
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tempmon_calib: calib@3c {
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reg = <0x3c 0x4>;
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};
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tempmon_temp_grade: temp-grade@10 {
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reg = <0x10 0x4>;
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};
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};
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tempmon: tempmon {
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compatible = "fsl,imx7d-tempmon";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tempmon =<&anatop>;
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nvmem-cells = <&tempmon_calib>,
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<&tempmon_temp_grade>;
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nvmem-cell-names = "calib", "temp_grade";
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clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
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};
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anatop: anatop@30360000 {
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@ -504,8 +556,11 @@
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reg = <0x30360000 0x10000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_1p0d: regulator-vdd1p0d {
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reg_1p0d: regulator-vdd1p0d@30360210 {
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reg = <0x30360210>;
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compatible = "fsl,anatop-regulator";
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regulator-name = "vdd1p0d";
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regulator-min-microvolt = <800000>;
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@ -516,6 +571,7 @@
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anatop-min-bit-val = <8>;
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anatop-min-voltage = <800000>;
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anatop-max-voltage = <1200000>;
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anatop-enable-bit = <0>;
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};
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};
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@ -529,12 +585,15 @@
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_SNVS_CLK>;
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clock-names = "snvs-rtc";
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};
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snvs_poweroff: snvs-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&snvs>;
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offset = <0x38>;
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value = <0x60>;
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mask = <0x60>;
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};
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@ -558,11 +617,32 @@
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};
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src: src@30390000 {
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compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
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compatible = "fsl,imx7d-src", "syscon";
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reg = <0x30390000 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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gpc: gpc@303a0000 {
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compatible = "fsl,imx7d-gpc";
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reg = <0x303a0000 0x10000>;
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interrupt-controller;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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#power-domain-cells = <1>;
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pgc {
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#address-cells = <1>;
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#size-cells = <0>;
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pgc_pcie_phy: pgc-power-domain@1 {
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#power-domain-cells = <0>;
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reg = <1>;
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power-supply = <®_1p0d>;
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};
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};
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};
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};
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aips2: aips-bus@30400000 {
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@ -609,7 +689,7 @@
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clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
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<&clks IMX7D_PWM1_ROOT_CLK>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -620,7 +700,7 @@
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clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
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<&clks IMX7D_PWM2_ROOT_CLK>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -631,7 +711,7 @@
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clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
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<&clks IMX7D_PWM3_ROOT_CLK>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -642,7 +722,7 @@
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clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
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<&clks IMX7D_PWM4_ROOT_CLK>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -664,118 +744,156 @@
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reg = <0x30800000 0x400000>;
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ranges;
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ecspi1: ecspi@30820000 {
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spba-bus@30800000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
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reg = <0x30820000 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
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<&clks IMX7D_ECSPI1_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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#size-cells = <1>;
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reg = <0x30800000 0x100000>;
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ranges;
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ecspi1: ecspi@30820000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
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reg = <0x30820000 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
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<&clks IMX7D_ECSPI1_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi2: ecspi@30830000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
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reg = <0x30830000 0x10000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
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<&clks IMX7D_ECSPI2_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi3: ecspi@30840000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
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reg = <0x30840000 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
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<&clks IMX7D_ECSPI3_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@30860000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30860000 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_UART1_ROOT_CLK>,
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<&clks IMX7D_UART1_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@30890000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30890000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_UART2_ROOT_CLK>,
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<&clks IMX7D_UART2_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart3: serial@30880000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30880000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_UART3_ROOT_CLK>,
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<&clks IMX7D_UART3_ROOT_CLK>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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sai1: sai@308a0000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
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reg = <0x308a0000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_SAI1_IPG_CLK>,
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<&clks IMX7D_SAI1_ROOT_CLK>,
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<&clks IMX7D_CLK_DUMMY>,
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<&clks IMX7D_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "rx", "tx";
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dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
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status = "disabled";
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};
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sai2: sai@308b0000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
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reg = <0x308b0000 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_SAI2_IPG_CLK>,
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<&clks IMX7D_SAI2_ROOT_CLK>,
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<&clks IMX7D_CLK_DUMMY>,
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<&clks IMX7D_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "rx", "tx";
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dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
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status = "disabled";
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};
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sai3: sai@308c0000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
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reg = <0x308c0000 0x10000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_SAI3_IPG_CLK>,
|
||||
<&clks IMX7D_SAI3_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ecspi2: ecspi@30830000 {
|
||||
crypto: caam@30900000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
#size-cells = <1>;
|
||||
reg = <0x30900000 0x40000>;
|
||||
ranges = <0 0x30900000 0x40000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CAAM_CLK>,
|
||||
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
|
||||
clock-names = "ipg", "aclk";
|
||||
|
||||
ecspi3: ecspi@30840000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
|
||||
<&clks IMX7D_ECSPI3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
sec_jr0: jr0@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART1_ROOT_CLK>,
|
||||
<&clks IMX7D_UART1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
sec_jr1: jr1@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART2_ROOT_CLK>,
|
||||
<&clks IMX7D_UART2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx7d-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_UART3_ROOT_CLK>,
|
||||
<&clks IMX7D_UART3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai1: sai@308a0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI1_IPG_CLK>,
|
||||
<&clks IMX7D_SAI1_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@308b0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI2_IPG_CLK>,
|
||||
<&clks IMX7D_SAI2_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai3: sai@308c0000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
||||
reg = <0x308c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_SAI3_IPG_CLK>,
|
||||
<&clks IMX7D_SAI3_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "rx", "tx";
|
||||
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
|
||||
status = "disabled";
|
||||
sec_jr2: jr1@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
flexcan1: can@30a00000 {
|
||||
@ -918,24 +1036,12 @@
|
||||
reg = <0x30b30200 0x200>;
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_PHY1_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop3: usbphynop3 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@30b40000 {
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
|
||||
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
|
||||
<&clks IMX7D_USDHC1_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
@ -946,8 +1052,8 @@
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
|
||||
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
|
||||
<&clks IMX7D_USDHC2_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
@ -958,8 +1064,8 @@
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
|
||||
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
|
||||
<&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
@ -980,9 +1086,11 @@
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupt-names = "int0", "int1", "int2", "pps";
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
|
||||
@ -995,5 +1103,36 @@
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dma_apbh: dma-apbh@33000000 {
|
||||
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
|
||||
reg = <0x33000000 0x2000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
};
|
||||
|
||||
gpmi: gpmi-nand@33002000{
|
||||
compatible = "fsl,imx7d-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bch";
|
||||
clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
|
||||
<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
clock-names = "gpmi_io", "gpmi_bch_apb";
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -80,10 +80,10 @@
|
||||
#define IMX7D_ARM_M4_ROOT_SRC 67
|
||||
#define IMX7D_ARM_M4_ROOT_CG 68
|
||||
#define IMX7D_ARM_M4_ROOT_DIV 69
|
||||
#define IMX7D_ARM_M0_ROOT_CLK 70
|
||||
#define IMX7D_ARM_M0_ROOT_SRC 71
|
||||
#define IMX7D_ARM_M0_ROOT_CG 72
|
||||
#define IMX7D_ARM_M0_ROOT_DIV 73
|
||||
#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
|
||||
#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
|
||||
#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
|
||||
#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
|
||||
#define IMX7D_MAIN_AXI_ROOT_CLK 74
|
||||
#define IMX7D_MAIN_AXI_ROOT_SRC 75
|
||||
#define IMX7D_MAIN_AXI_ROOT_CG 76
|
||||
@ -450,5 +450,10 @@
|
||||
#define IMX7D_CLK_ARM 437
|
||||
#define IMX7D_CKIL 438
|
||||
#define IMX7D_OCOTP_CLK 439
|
||||
#define IMX7D_CLK_END 440
|
||||
#define IMX7D_NAND_RAWNAND_CLK 440
|
||||
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
|
||||
#define IMX7D_SNVS_CLK 442
|
||||
#define IMX7D_CAAM_CLK 443
|
||||
#define IMX7D_KPP_ROOT_CLK 444
|
||||
#define IMX7D_CLK_END 445
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
||||
16
include/dt-bindings/power/imx7-power.h
Normal file
16
include/dt-bindings/power/imx7-power.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Impinj
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX7_POWER_H__
|
||||
#define __DT_BINDINGS_IMX7_POWER_H__
|
||||
|
||||
#define IMX7_POWER_DOMAIN_MIPI_PHY 0
|
||||
#define IMX7_POWER_DOMAIN_PCIE_PHY 1
|
||||
#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user