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sunxi: H616: DRAM: Adjust size scan procedure

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It's safer to start scanning for columns first and then rows. Columns
reside on LSB address pins, which means that second configuration will
already have all needed row pins active.

This is also preparation for introducing DDR4 support, which need scan
for banks and bank groups too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
This commit is contained in:
Jernej Skrabec 2024-08-30 10:55:09 -05:00 committed by Andre Przywara
parent d88668f913
commit b37edefc20
1 changed files with 21 additions and 16 deletions
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37
arch/arm/mach-sunxi/dram_sun50i_h616.c
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@ -1362,28 +1362,33 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para,
static void mctl_auto_detect_dram_size(const struct dram_para *para, static void mctl_auto_detect_dram_size(const struct dram_para *para,
struct dram_config *config) struct dram_config *config)
{ {
/* detect row address bits */ unsigned int shift;
config->cols = 8;
/* max. config for columns, but not rows */
config->cols = 11;
config->rows = 13;
mctl_core_init(para, config);
shift = config->bus_full_width + 1;
/* detect column address bits */
for (config->cols = 8; config->cols < 11; config->cols++) {
if (mctl_mem_matches(1ULL << (config->cols + shift)))
break;
}
debug("detected %u columns\n", config->cols);
/* reconfigure to make sure that all active rows are accessible */
config->rows = 18; config->rows = 18;
mctl_core_init(para, config); mctl_core_init(para, config);
/* detect row address bits */
shift = config->bus_full_width + 4 + config->cols;
for (config->rows = 13; config->rows < 18; config->rows++) { for (config->rows = 13; config->rows < 18; config->rows++) {
/* 8 banks, 8 bit per byte and 16/32 bit width */ if (mctl_mem_matches(1ULL << (config->rows + shift)))
if (mctl_mem_matches((1 << (config->rows + config->cols +
4 + config->bus_full_width))))
break;
}
/* detect column address bits */
config->cols = 11;
mctl_core_init(para, config);
for (config->cols = 8; config->cols < 11; config->cols++) {
/* 8 bits per byte and 16/32 bit width */
if (mctl_mem_matches(1 << (config->cols + 1 +
config->bus_full_width)))
break; break;
} }
debug("detected %u rows\n", config->rows);
} }
static unsigned long mctl_calc_size(const struct dram_config *config) static unsigned long mctl_calc_size(const struct dram_config *config)