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ram: k3-ddrss: Fix register name and explain its usage

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The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
default that says 8 GB, which the AM64x DDR controller wouldn't support).

The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
was that of the next register at offset 0x24.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
This commit is contained in:
Dominic Rath 2022-04-06 11:56:47 +02:00 committed by Tom Rini
parent 246e03476b
commit b4c80f245b
1 changed files with 3 additions and 3 deletions
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6
drivers/ram/k3-ddrss/k3-ddrss.c
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@ -30,7 +30,7 @@
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_V2A_CTL_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
#define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0)
@ -620,8 +620,8 @@ static int k3_ddrss_probe(struct udevice *dev)
return ret;
#ifdef CONFIG_K3_AM64_DDRSS
writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
/* AM64x supports only up to 2 GB SDRAM */
writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
#endif