Fixes for 2022.07

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12541
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Merge tag 'u-boot-imx-20220628' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2022.07

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12541

arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi

@@ -25,6 +25,23 @@
 	};
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+
 &i2c1 {
 	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;

arch/arm/mach-imx/imx8m/Kconfig

@@ -107,6 +107,9 @@ config TARGET_KONTRON_MX8MM
 	select IMX8MM
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MN_BSH_SMM_S2
 	bool "imx8mn-bsh-smm-s2"

arch/arm/mach-imx/imx8m/soc.c

@@ -1203,6 +1203,48 @@ static int cleanup_nodes_for_efi(void *blob)
 	return 0;
 }
 
+static int fixup_thermal_trips(void *blob, const char *name)
+{
+	int minc, maxc;
+	int node, trip;
+
+	node = fdt_path_offset(blob, "/thermal-zones");
+	if (node < 0)
+		return node;
+
+	node = fdt_subnode_offset(blob, node, name);
+	if (node < 0)
+		return node;
+
+	node = fdt_subnode_offset(blob, node, "trips");
+	if (node < 0)
+		return node;
+
+	get_cpu_temp_grade(&minc, &maxc);
+
+	fdt_for_each_subnode(trip, blob, node) {
+		const char *type;
+		int temp, ret;
+
+		type = fdt_getprop(blob, trip, "type", NULL);
+		if (!type)
+			continue;
+
+		temp = 0;
+		if (!strcmp(type, "critical"))
+			temp = 1000 * maxc;
+		else if (!strcmp(type, "passive"))
+			temp = 1000 * (maxc - 10);
+		if (temp) {
+			ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 #ifdef CONFIG_IMX8MQ
@@ -1345,6 +1387,13 @@ usb_modify_speed:
 #endif
 
 	cleanup_nodes_for_efi(blob);
+
+	if (fixup_thermal_trips(blob, "cpu-thermal"))
+		printf("Failed to update cpu-thermal trip(s)");
+	if (IS_ENABLED(CONFIG_IMX8MP) &&
+	    fixup_thermal_trips(blob, "soc-thermal"))
+		printf("Failed to update soc-thermal trip(s)");
+
 	return 0;
 }
 #endif

arch/arm/mach-imx/mx6/ddr.c

@@ -1469,8 +1469,17 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mprddqby3dl, 0x33333333);
 	}
 
-	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
+	/*
-	val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	 * MMDC Termination: rtt_nom:2 RZQ/2(120ohm),
+	 *                   rtt_nom:1 RZQ/4(60ohm),
+	 *                   rtt_nom:0 Disabled
+	 */
+	if (sysinfo->rtt_nom == 0)
+		val = 0x00000000;
+	else if (sysinfo->rtt_nom == 2)
+		val = 0x00011117;
+	else
+		val = 0x00022227;
 	mmdc0->mpodtctrl = val;
 	if (sysinfo->dsize > 1)
 		MMDC1(mpodtctrl, val);

board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c

@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <i2c_eeprom.h>
 #include <malloc.h>
 #include <net.h>
@@ -104,7 +105,15 @@ int board_init(void)
 
 int board_late_init(void)
 {
+	struct udevice *dev;
+	int ret;
+
 	setup_boot_device();
 	setup_mac_address();
+
+	ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev);
+	if (ret)
+		printf("Error bringing up USB hub (%d)\n", ret);
+
 	return 0;
 }

board/kontron/sl-mx8mm/spl.c

@@ -13,6 +13,9 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
 #include <hang.h>
 #include <i2c.h>
 #include <init.h>
@@ -213,6 +216,12 @@ void spl_board_init(void)
 	struct udevice *dev;
 	int ret;
 
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize %s: %d\n", dev->name, ret);
+	}
+
 	puts("Normal Boot\n");
 
 	ret = uclass_get_device_by_name(UCLASS_CLK,

board/toradex/apalis_imx6/apalis_imx6.c

@@ -771,244 +771,6 @@ void ldo_mode_set(int ldo_bypass)
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
 
-static int mx6_com_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x128mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x555A7954,
-MX6_MMDC_P0_MDCFG1, 0xDB328F64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x005A1023,
-MX6_MMDC_P0_MDOTC, 0x09555050,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000027,
-MX6_MMDC_P0_MDCTL, 0x831A0000,
-MX6_MMDC_P0_MDSCR, 0x04088032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00428031,
-MX6_MMDC_P0_MDSCR, 0x19308030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
-MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
-MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
-MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
-MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static int mx6_it_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x256mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x898E78f5,
-MX6_MMDC_P0_MDCFG1, 0xff328f64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x008E1023,
-MX6_MMDC_P0_MDOTC, 0x09444040,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000047,
-MX6_MMDC_P0_MDCTL, 0x841A0000,
-MX6_MMDC_P0_MDSCR, 0x02888032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x19408030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00007800,
-MX6_MMDC_P0_MPODTCTRL, 0x00022227,
-MX6_MMDC_P1_MPODTCTRL, 0x00022227,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
-MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
-MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
-MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
-MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -1024,36 +786,198 @@ static void ccgr_init(void)
 /*
  * Setup CCM_CCOSR register as follows:
  *
- * cko1_en  = 1	   --> CKO1 enabled
+ * clko2_en  = 1     --> CKO2 enabled
- * cko1_div = 111  --> divide by 8
+ * clko2_div = 000   --> divide by 1
- * cko1_sel = 1011 --> ahb_clk_root
+ * clko2_sel = 01110 --> osc_clk (24MHz)
  *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ * clk_out_sel = 1   --> Output CKO2 to CKO1
+ *
+ * This sets both CLKO2/CLKO1 output to 24MHz,
+ * CLKO1 configuration not relevant because of clk_out_sel
+ * (CLKO1 set to default)
  */
-	writel(0x000000FB, &ccm->ccosr);
+	writel(0x010E0101, &ccm->ccosr);
 }
 
-static void ddr_init(int *table, int size)
-{
-	int i;
 
-	for (i = 0; i < size / 2 ; i++)
+#define PAD_CTL_INPUT_DDR BIT(17)
-		writel(table[2 * i + 1], table[2 * i]);
+
-}
+struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	/* Differential input, 40 ohm DSE */
+	.dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+
+	/* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+
+	.dram_sdba2 = 0x00000000,
+
+	/* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */
+	.dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000,
+	.dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000,
+
+	/* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
+	.dram_sdqs0 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs1 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs2 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs3 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs4 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs5 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs6 = PAD_CTL_DSE_40ohm,
+	.dram_sdqs7 = PAD_CTL_DSE_40ohm,
+
+	/* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
+	.dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+	.dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
+};
+
+struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = 0x000C0000,
+
+	/* SDQS[0:7]: Differential input */
+	.grp_ddrmode_ctl = PAD_CTL_INPUT_DDR,
+
+	/* DATA[0:63]: Pull/Keeper disabled */
+	.grp_ddrpke = 0,
+
+	/* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */
+	.grp_addds = PAD_CTL_DSE_40ohm,
+
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */
+	.grp_ctlds = PAD_CTL_DSE_40ohm,
+
+	/* DATA[0:63]: Differential input */
+	.grp_ddrmode = PAD_CTL_INPUT_DDR,
+
+	/* DATA[0:63]: 40 ohm DSE */
+	.grp_b0ds = PAD_CTL_DSE_40ohm,
+	.grp_b1ds = PAD_CTL_DSE_40ohm,
+	.grp_b2ds = PAD_CTL_DSE_40ohm,
+	.grp_b3ds = PAD_CTL_DSE_40ohm,
+	.grp_b4ds = PAD_CTL_DSE_40ohm,
+	.grp_b5ds = PAD_CTL_DSE_40ohm,
+	.grp_b6ds = PAD_CTL_DSE_40ohm,
+	.grp_b7ds = PAD_CTL_DSE_40ohm,
+};
+
+struct mx6_ddr_sysinfo sysinfo = {
+	.dsize = 2,         /* width of data bus: 2=64 */
+	.cs_density = 32,   /* full range so that get_mem_size() works, 32Gb per CS */
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,        /* Dynamic ODT, RZQ/2 */
+	.rtt_nom = 0,       /* Disabled */
+	.walat = 0,         /* Write additional latency */
+	.ralat = 5,         /* Read additional latency */
+	.mif3_mode = 3,     /* Command prediction working mode */
+	.bi_on = 1,         /* Bank interleaving enabled */
+	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+	.pd_fast_exit = 1,  /* enable precharge power-down fast exit */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,        /* Refresh cycles at 32KHz */
+	.refr = 3,          /* 4 refresh commands per refresh cycle */
+};
+
+static const struct mx6_mmdc_calibration mx6_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0009000E,
+	.p0_mpwldectrl1 = 0x0018000B,
+	.p1_mpwldectrl0 = 0x00060015,
+	.p1_mpwldectrl1 = 0x0006000E,
+	.p0_mpdgctrl0 = 0x432A0338,
+	.p0_mpdgctrl1 = 0x03260324,
+	.p1_mpdgctrl0 = 0x43340344,
+	.p1_mpdgctrl1 = 0x031E027C,
+	.p0_mprddlctl = 0x33272D2E,
+	.p1_mprddlctl = 0x2F312B37,
+	.p0_mpwrdlctl = 0x3A35433C,
+	.p1_mpwrdlctl = 0x4336453F,
+};
+
+static const struct mx6_ddr3_cfg ddr3_cfg = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1312,
+	.trcmin = 4812,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+struct mx6_ddr_sysinfo sysinfo_it = {
+	.dsize = 2,         /* width of data bus: 2=64 */
+	.cs_density = 32,   /* full range so that get_mem_size() works, 32Gb per CS */
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 1,        /* Dynamic ODT, RZQ/4 */
+	.rtt_nom = 1,       /* RZQ/4 */
+	.walat = 0,         /* Write additional latency */
+	.ralat = 5,         /* Read additional latency */
+	.mif3_mode = 3,     /* Command prediction working mode */
+	.bi_on = 1,         /* Bank interleaving enabled */
+	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+	.pd_fast_exit = 1,  /* enable precharge power-down fast exit */
+	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 1,        /* Refresh cycles at 32KHz */
+	.refr = 7,          /* 8 refresh commands per refresh cycle */
+};
+
+static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = {
+	.p0_mpwldectrl0 = 0x0009000E,
+	.p0_mpwldectrl1 = 0x0018000B,
+	.p1_mpwldectrl0 = 0x00060015,
+	.p1_mpwldectrl1 = 0x0006000E,
+	.p0_mpdgctrl0 = 0x03300338,
+	.p0_mpdgctrl1 = 0x03240324,
+	.p1_mpdgctrl0 = 0x03440350,
+	.p1_mpdgctrl1 = 0x032C0308,
+	.p0_mprddlctl = 0x40363C3E,
+	.p1_mprddlctl = 0x3C3E3C46,
+	.p0_mpwrdlctl = 0x403E463E,
+	.p1_mpwrdlctl = 0x4A384C46,
+};
+
+static const struct mx6_ddr3_cfg ddr3_cfg_it = {
+	.mem_speed = 1066,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1312,
+	.trcmin = 4812,
+	.trasmin = 3500,
+	.SRT = 1,
+};
+
 
 /* Perform DDR DRAM calibration */
-static void spl_dram_perform_cal(void)
+static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
 {
 #ifdef CONFIG_MX6_DDRCAL
 	int err;
-	struct mx6_ddr_sysinfo ddr_sysinfo = {
-		.dsize = 2,
-	};
 
-	err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+	err = mmdc_do_write_level_calibration(ddr_sysinfo);
 	if (err)
 		printf("error %d from write level calibration\n", err);
-	err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+	err = mmdc_do_dqs_calibration(ddr_sysinfo);
 	if (err)
 		printf("error %d from dqs calibration\n", err);
 #endif
@@ -1061,23 +985,35 @@ static void spl_dram_perform_cal(void)
 
 static void spl_dram_init(void)
 {
-	int minc, maxc;
+	bool temp_grade_it;
 
-	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	switch (get_cpu_temp_grade(NULL, NULL)) {
 	case TEMP_COMMERCIAL:
 	case TEMP_EXTCOMMERCIAL:
 		puts("Commercial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
+		temp_grade_it = false;
 		break;
 	case TEMP_INDUSTRIAL:
 	case TEMP_AUTOMOTIVE:
 	default:
 		puts("Industrial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
+		temp_grade_it = true;
 		break;
 	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+
+	if (temp_grade_it)
+		mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it);
+	else
+		mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg);
+
 	udelay(100);
-	spl_dram_perform_cal();
+
+	if (temp_grade_it)
+		spl_dram_perform_cal(&sysinfo_it);
+	else
+		spl_dram_perform_cal(&sysinfo);
 }
 
 void board_init_f(ulong dummy)

board/toradex/colibri_imx6/colibri_imx6.c

@@ -980,13 +980,17 @@ static void ccgr_init(void)
 /*
  * Setup CCM_CCOSR register as follows:
  *
- * cko1_en  = 1	   --> CKO1 enabled
+ * clko2_en  = 1     --> CKO2 enabled
- * cko1_div = 111  --> divide by 8
+ * clko2_div = 000   --> divide by 1
- * cko1_sel = 1011 --> ahb_clk_root
+ * clko2_sel = 01110 --> osc_clk (24MHz)
  *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ * clk_out_sel = 1   --> Output CKO2 to CKO1
+ *
+ * This sets both CLKO2/CLKO1 output to 24MHz,
+ * CLKO1 configuration not relevant because of clk_out_sel
+ * (CLKO1 set to default)
  */
-	writel(0x000000FB, &ccm->ccosr);
+	writel(0x010E0101, &ccm->ccosr);
 }
 
 static void ddr_init(int *table, int size)

configs/imx8mm_data_modul_edm_sbc_defconfig

@@ -156,6 +156,7 @@ CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 # CONFIG_INPUT is not set
 CONFIG_MISC=y
+CONFIG_USB_HUB_USB251XB=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_SUPPORT_EMMC_BOOT=y

configs/kontron-sl-mx8mm_defconfig

@@ -16,6 +16,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_KONTRON_MX8MM=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x42000000
@@ -99,6 +100,7 @@ CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_PCA9450=y
 CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_CONS_INDEX=2

drivers/power/pmic/pca9450.c

@@ -7,9 +7,12 @@
 #include <fdtdec.h>
 #include <errno.h>
 #include <dm.h>
+#include <dm/device_compat.h>
 #include <i2c.h>
+#include <linux/err.h>
 #include <log.h>
 #include <asm/global_data.h>
+#include <asm-generic/gpio.h>
 #include <power/pmic.h>
 #include <power/regulator.h>
 #include <power/pca9450.h>
@@ -26,6 +29,10 @@ static const struct pmic_child_info pmic_children_info[] = {
 	{ },
 };
 
+struct pca9450_priv {
+	struct gpio_desc *sd_vsel_gpio;
+};
+
 static int pca9450_reg_count(struct udevice *dev)
 {
 	return PCA9450_REG_NUM;
@@ -76,6 +83,24 @@ static int pca9450_bind(struct udevice *dev)
 	return 0;
 }
 
+static int pca9450_probe(struct udevice *dev)
+{
+	struct pca9450_priv *priv = dev_get_priv(dev);
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) {
+		priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel",
+							     GPIOD_IS_OUT |
+							     GPIOD_IS_OUT_ACTIVE);
+		if (IS_ERR(priv->sd_vsel_gpio)) {
+			ret = PTR_ERR(priv->sd_vsel_gpio);
+			dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret);
+		}
+	}
+
+	return ret;
+}
+
 static struct dm_pmic_ops pca9450_ops = {
 	.reg_count = pca9450_reg_count,
 	.read = pca9450_read,
@@ -94,5 +119,7 @@ U_BOOT_DRIVER(pmic_pca9450) = {
 	.id = UCLASS_PMIC,
 	.of_match = pca9450_ids,
 	.bind = pca9450_bind,
+	.probe = pca9450_probe,
 	.ops = &pca9450_ops,
+	.priv_auto = sizeof(struct pca9450_priv),
 };

include/configs/imx8mm_data_modul_edm_sbc.h

@@ -71,7 +71,6 @@
 		"mtd nor0=sf raw 0x0 0x1000000\0"			\
 	"dmo_preboot="							\
 		"sf probe ; " /* Scan for SPI NOR, needed by DFU */	\
-		"run dmo_usb_start_hub ; "				\
 		/* Attempt to start USB and Network console */		\
 		"run dmo_usb_cdc_acm_start ; "				\
 		"run dmo_netconsole_start\0"				\
@@ -91,25 +90,6 @@
 				"setenv stdin ${stdin},usbacm ; "	\
 			"fi ; "						\
 		"fi\0"							\
-	"dmo_usb_start_hub="						\
-		"i2c dev 1 ; "						\
-		/* Reset the USB USB */					\
-		"gpio clear GPIO5_2 ; sleep 0.01 ; " /* t1 > 1us */	\
-		"gpio set GPIO5_2 ; sleep 0.01 ; " /* t5 > 3us */	\
-		/* Write chunks of descriptor into the USB HUB */	\
-		"mw.l 0x7e1000 0x14042417 ; mw.l 0x7e1004 0x9b0bb325 ; "\
-		"mw.l 0x7e1008 0x00000220 ; mw.l 0x7e100c 0x01320100 ; "\
-		"mw.l 0x7e1010 0x00003232 ; mw.l 0x7e1014 0x4d000909 ; "\
-		"i2c write 0x7e1000 0x2c 0x00 0x18 -s ; "		\
-		"mw.l 0x7e1000 0x6300690f ; mw.l 0x7e1004 0x6f007200 ; "\
-		"mw.l 0x7e1008 0x68006300 ; mw.l 0x7e100c 0x70006900 ; "\
-		"i2c write 0x7e1000 0x2c 0x18 0x10 -s ; "		\
-		"mw.l 0x7e1000 0x53005511 ; mw.l 0x7e1004 0x32004200 ; "\
-		"mw.l 0x7e1008 0x31003500 ; mw.l 0x7e100c 0x42003400 ; "\
-		"mw.l 0x7e1010 0x00006900 ; "				\
-		"i2c write 0x7e1000 0x2c 0x54 0x12 -s ; "		\
-		"mw.l 0x7e1000 0x00000101 ; "				\
-		"i2c write 0x7e1000 0x2c 0xff 0x2 -s\0"			\
 	"dmo_netconsole_start="						\
 		"if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\
 			"setenv autoload false && "			\