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Merge tag 'u-boot-imx-next-20240823' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22098

- Add BOOTAUX support for apalis and colibri imx8 boards.
- Cleanup tqma6 board by removing unneeded board code.
- Add support for booting from ecspi3 via bmode command on imx6.
- Add a script to ease updating flash.bin on imx8mm phytec board.
- Enable cat and xxd commands on Data Modul i.MX8M Mini/Plus eDM SBC and
  use USB SDPS as fallback option.
- Fix critical temperature on imx9.
- Add Cortex M and bootaux support for phycore-imx8mp.
This commit is contained in:
Tom Rini 2024-08-23 15:00:29 -06:00
commit b8f0f8db23
15 changed files with 53 additions and 195 deletions
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16
arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
View File

@ -10,6 +10,22 @@
};
};
&aips2 {
bootph-all;
};
&pinctrl_uart2 {
bootph-all;
};
&soc {
bootph-all;
};
&uart2 {
bootph-all;
};
&wdog1 {
bootph-pre-ram;
};

2
arch/arm/mach-imx/imx9/soc.c
View File

@ -536,7 +536,7 @@ static int fixup_thermal_trips(void *blob, const char *name)
temp = 0;
if (!strcmp(type, "critical"))
temp = 1000 * (maxc - 5);
temp = 1000 * maxc;
else if (!strcmp(type, "passive"))
temp = 1000 * (maxc - 10);
if (temp) {

4
arch/arm/mach-imx/mx6/soc.c
View File

@ -585,6 +585,10 @@ const struct boot_mode soc_boot_modes[] = {
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
{"ecspi3:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0a)},
{"ecspi3:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x1a)},
{"ecspi3:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x2a)},
{"ecspi3:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x3a)},
/* 4 bit bus width */
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},

5
board/data_modul/imx8mp_edm_sbc/spl.c
View File

@ -100,7 +100,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
if (boot_dev_spl == MMC3_BOOT) /* eMMC */
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1; /* SD */
if (boot_dev_spl == SD2_BOOT) /* SD */
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_BOOTROM; /* USB SDPS */
}
void board_boot_order(u32 *spl_boot_list)

5
board/phytec/phycore_imx8mp/phycore_imx8mp.env
View File

@ -30,7 +30,7 @@ ip_dyn=yes
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
mmcargs=
setenv bootargs console=${console}
setenv bootargs ${mcore_clk} console=${console}
root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
mmcautodetect=yes
mmcboot=
@ -51,7 +51,7 @@ mmcdev=CONFIG_SYS_MMC_ENV_DEV
mmcpart=1
mmcroot=2
netargs=
setenv bootargs console=${console} root=/dev/nfs ip=dhcp
setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp
nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=
echo Booting from net ...;
@ -74,4 +74,5 @@ netboot=
echo WARN: Cannot load the DT;
fi;
nfsroot=/srv/nfs
prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted
sd_dev=1

8
board/toradex/apalis-imx8/apalis-imx8.c
View File

@ -290,6 +290,14 @@ int board_init(void)
return 0;
}
void reset_cpu(void)
{
sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
do {
} while (1);
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

126
board/tq/tqma6/tqma6.c
View File

@ -19,33 +19,15 @@
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/spi.h>
#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
#include <spi_flash.h>
#include "tqma6_bb.h"
DECLARE_GLOBAL_DATA_PTR;
#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -55,114 +37,6 @@ int dram_init(void)
static const uint16_t tqma6_emmc_dsr = 0x0100;
#ifndef CONFIG_DM_MMC
/* eMMC on USDHCI3 always present */
static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
/* eMMC reset */
NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
};
/*
* According to board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 eMMC (SD3) on TQMa6
* mmc1 .. n optional slots used on baseboard
*/
struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
.esdhc_base = USDHC3_BASE_ADDR,
.max_bus_width = 8,
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is always present */
ret = 1;
else
ret = tqma6_bb_board_mmc_getcd(mmc);
return ret;
}
int board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is always present */
ret = 0;
else
ret = tqma6_bb_board_mmc_getwp(mmc);
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
ARRAY_SIZE(tqma6_usdhc3_pads));
tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
puts("Warning: failed to initialize eMMC dev\n");
} else {
struct mmc *mmc = find_mmc_device(0);
if (mmc)
mmc_set_dsr(mmc, tqma6_emmc_dsr);
}
tqma6_bb_board_mmc_init(bis);
return 0;
}
#endif
#ifndef CONFIG_DM_SPI
static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
/* SS1 */
NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
};
#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
static unsigned const tqma6_ecspi1_cs[] = {
TQMA6_SF_CS_GPIO,
};
__weak void tqma6_iomuxc_spi(void)
{
unsigned i;
for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
gpio_direction_output(tqma6_ecspi1_cs[i], 1);
imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
ARRAY_SIZE(tqma6_ecspi1_pads));
}
#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return ((bus == CONFIG_SF_DEFAULT_BUS) &&
(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
}
#endif
#endif
int board_early_init_f(void)
{

35
board/tq/tqma6/tqma6_mba6.c
View File

@ -31,28 +31,6 @@
#include "tqma6_bb.h"
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#if defined(CONFIG_TQMA6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
@ -89,17 +67,6 @@ static void mba6_setup_iomuxc_enet(void)
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
}
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
};
static void mba6_setup_iomuxc_uart(void)
{
imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
ARRAY_SIZE(mba6_uart2_pads));
}
int board_mmc_get_env_dev(int devno)
{
/*
@ -159,8 +126,6 @@ int board_phy_config(struct phy_device *phydev)
int tqma6_bb_board_early_init_f(void)
{
mba6_setup_iomuxc_uart();
return 0;
}

1
configs/apalis-imx8_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95400000
CONFIG_SYS_MEMTEST_START=0x88000000

2
configs/colibri-imx8x_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_IMX_SNVS_SEC_SC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95c00000
CONFIG_SYS_MEMTEST_START=0x88000000

2
configs/imx8mm_data_modul_edm_sbc_defconfig
View File

@ -105,6 +105,8 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y

2
configs/imx8mp_data_modul_edm_sbc_defconfig
View File

@ -112,6 +112,8 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y

1
configs/phycore-imx8mp_defconfig
View File

@ -24,6 +24,7 @@ CONFIG_SPL_BSS_START_ADDR=0x98fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3e0000
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y

31
include/configs/gw_ventana.h
View File

@ -6,55 +6,26 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/* SPL */
/* Location in NAND to read U-Boot from */
/* Falcon Mode */
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
#include "mx6_common.h"
/* Serial */
#define CFG_MXC_UART_BASE UART2_BASE
/* NAND */
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
/*
* PCI express
*/
/*
* PMIC
*/
/* PMIC */
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#define CFG_POWER_LTC3676_I2C_ADDR 0x3c
/* Various command support */
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Miscellaneous configurable options */
/* Memory configuration */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* MTD Command for mtdparts
*/
/* Persistent Environment Config */
/* Environment */
#endif /* __CONFIG_H */

8
include/configs/phycore_imx8mm.h
View File

@ -29,6 +29,14 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \
"update_offset=0x42\0" \
"update_filename=flash.bin\0" \
"update_bootimg=" \
"mmc dev ${mmcdev} ; " \
"if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
"fi\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \