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Convert CONFIG_SYS_SPD_BUS_NUM to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_SPD_BUS_NUM

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-15 12:03:54 -04:00
parent 1f7e2fc324
commit bca4509d57
75 changed files with 52 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
README
View File

@ -1302,11 +1302,6 @@ The following options need to be configured:
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CONFIG_SYS_SPD_BUS_NUM
If defined, then this indicates the I2C bus number for DDR SPD.
If not defined, then U-Boot assumes that SPD is on I2C bus 0.
CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC. If defined, then this indicates the I2C bus number for the RTC.

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -80,6 +80,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_COMMON_INIT_DDR=y CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -69,6 +69,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_NAND_defconfig
View File

@ -79,6 +79,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_NOR_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_COMMON_INIT_DDR=y CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y

1
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -68,6 +68,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -71,6 +71,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -81,6 +81,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_36BIT_NOR_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_COMMON_INIT_DDR=y CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -73,6 +73,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_NAND_defconfig
View File

@ -80,6 +80,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_NOR_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_COMMON_INIT_DDR=y CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y

1
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -69,6 +69,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -78,6 +78,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_BR0_PRELIM=0xFF800C21

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -68,6 +68,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -71,6 +71,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PC_36BIT_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PC_NAND_defconfig
View File

@ -77,6 +77,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_BR0_PRELIM=0xFF800C21

1
configs/P1020RDB-PC_SDCARD_defconfig
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@ -67,6 +67,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PC_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P1020RDB-PD_NAND_defconfig
View File

@ -80,6 +80,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_BR0_PRELIM=0xFF800C21

1
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_BR0_PRELIM=0xEC001001

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -73,6 +73,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_BR0_PRELIM=0xEC001001

1
configs/P1020RDB-PD_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_BR0_PRELIM=0xEC001001

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -82,6 +82,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_BR0_PRELIM=0xFF800C21

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -75,6 +75,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P2020RDB-PC_36BIT_defconfig
View File

@ -51,6 +51,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P2020RDB-PC_NAND_defconfig
View File

@ -81,6 +81,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_BR0_PRELIM=0xFF800C21

1
configs/P2020RDB-PC_SDCARD_defconfig
View File

@ -71,6 +71,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View File

@ -74,6 +74,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P2020RDB-PC_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_BR0_PRELIM=0xEF001001

1
configs/P3041DS_NAND_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P3041DS_SDCARD_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P3041DS_SPIFLASH_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P3041DS_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P4080DS_SDCARD_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P4080DS_SPIFLASH_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P4080DS_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y CONFIG_DM=y
CONFIG_LBA48=y CONFIG_LBA48=y
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P5040DS_NAND_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P5040DS_SDCARD_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P5040DS_SPIFLASH_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

1
configs/P5040DS_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_DM=y
CONFIG_FSL_SATA_V2=y CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y CONFIG_FSL_CAAM=y
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_DDR_ECC=y CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM_BOOL=y

5
drivers/ddr/Kconfig
View File

@ -30,5 +30,10 @@ config DDR_SPD
For memory controllers that can utilize it, add enable support for For memory controllers that can utilize it, add enable support for
using the JEDEC SDP standard. using the JEDEC SDP standard.
config SYS_SPD_BUS_NUM
int "I2C bus number for DDR SPD"
depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY
default 0
source "drivers/ddr/altera/Kconfig" source "drivers/ddr/altera/Kconfig"
source "drivers/ddr/imx/Kconfig" source "drivers/ddr/imx/Kconfig"

2
include/configs/MPC8548CDS.h
View File

@ -263,8 +263,6 @@
*/ */
#if !CONFIG_IS_ENABLED(DM_I2C) #if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#else
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif #endif
/* EEPROM */ /* EEPROM */

1
include/configs/P1010RDB.h
View File

@ -110,7 +110,6 @@
/* DDR Setup */ /* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52 #define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/P2041RDB.h
View File

@ -89,7 +89,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52 #define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

1
include/configs/T102xRDB.h
View File

@ -126,7 +126,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB) #if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB) #elif defined(CONFIG_TARGET_T1023RDB)

1
include/configs/T104xRDB.h
View File

@ -106,7 +106,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

1
include/configs/T208xQDS.h
View File

@ -95,7 +95,6 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS2 0x52

1
include/configs/T208xRDB.h
View File

@ -90,7 +90,6 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS2 0x52

1
include/configs/T4240RDB.h
View File

@ -178,7 +178,6 @@
/* /*
* DDR Setup * DDR Setup
*/ */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS2 0x54
#define SPD_EEPROM_ADDRESS3 0x56 #define SPD_EEPROM_ADDRESS3 0x56

1
include/configs/corenet_ds.h
View File

@ -92,7 +92,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */

1
include/configs/km/pg-wcom-ls102xa.h
View File

@ -22,7 +22,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */ /* POST memory regions test */

1
include/configs/kmcent2.h
View File

@ -171,7 +171,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

1
include/configs/ls1021aqds.h
View File

@ -23,7 +23,6 @@
#endif #endif
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifndef CONFIG_SYS_FSL_DDR4 #ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DDR_RAW_TIMING

1
include/configs/ls1043aqds.h
View File

@ -13,7 +13,6 @@
/* Physical Memory Map */ /* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifdef CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef

2
include/configs/ls1043ardb.h
View File

@ -12,8 +12,6 @@
/* Physical Memory Map */ /* Physical Memory Map */
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifndef CONFIG_SPL #ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/ls1046aqds.h
View File

@ -13,7 +13,6 @@
/* Physical Memory Map */ /* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifdef CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/ls1046ardb.h
View File

@ -14,7 +14,6 @@
/* Physical Memory Map */ /* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/ls1088aqds.h
View File

@ -16,7 +16,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
/* /*

1
include/configs/ls1088ardb.h
View File

@ -17,7 +17,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)

1
include/configs/ls2080aqds.h
View File

@ -24,7 +24,6 @@
#define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS5 0x55
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)

1
include/configs/ls2080ardb.h
View File

@ -29,7 +29,6 @@
#define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS5 0x55
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)

1
include/configs/lx2160a_common.h
View File

@ -31,7 +31,6 @@
#define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS5 0x55
#define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS6 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_SYS_MONITOR_LEN (936 * 1024) #define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */

1
include/configs/novena.h
View File

@ -39,7 +39,6 @@
/* I2C */ /* I2C */
#define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_SPD_BUS_NUM 0
/* I2C EEPROM */ /* I2C EEPROM */

3
include/configs/p1_p2_rdb_pc.h
View File

@ -116,7 +116,6 @@
/* DDR Setup */ /* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52 #define SPD_EEPROM_ADDRESS 0x52
#if defined(CONFIG_TARGET_P1020RDB_PD) #if defined(CONFIG_TARGET_P1020RDB_PD)
@ -346,8 +345,6 @@
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#endif #endif
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
/* /*
* I2C2 EEPROM * I2C2 EEPROM
*/ */

2
include/configs/socrates.h
View File

@ -118,8 +118,6 @@
#define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_SPD_BUS_NUM 0
/* /*
* General PCI * General PCI
* Memory space is mapped 1-1. * Memory space is mapped 1-1.

1
include/configs/vf610twr.h
View File

@ -26,7 +26,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_FEC_MXC_PHYADDR 0
/* I2C Configs */ /* I2C Configs */
#define CONFIG_SYS_SPD_BUS_NUM 0
/* /*
* We do have 128MB of memory on the Vybrid Tower board. Leave the last * We do have 128MB of memory on the Vybrid Tower board. Leave the last

3
include/i2c.h
View File

@ -647,9 +647,6 @@ void i2c_early_init_f(void);
#if !defined(CONFIG_SYS_RTC_BUS_NUM) #if !defined(CONFIG_SYS_RTC_BUS_NUM)
#define CONFIG_SYS_RTC_BUS_NUM 0 #define CONFIG_SYS_RTC_BUS_NUM 0
#endif #endif
#if !defined(CONFIG_SYS_SPD_BUS_NUM)
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
struct i2c_adapter { struct i2c_adapter {
void (*init)(struct i2c_adapter *adap, int speed, void (*init)(struct i2c_adapter *adap, int speed,