mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 14:00:19 +00:00
Merge branch 'mpc86xx'
This commit is contained in:
Jon Loeliger
commit
bdee35d0e0
@ -55,7 +55,7 @@
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memory {
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memory {
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device_type = "memory";
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device_type = "memory";
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linux,phandle = <300>;
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linux,phandle = <300>;
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reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot
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reg = <00000000 40000000>; // 1G at 0x0
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};
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};
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soc8641@f8000000 {
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soc8641@f8000000 {
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@ -95,28 +95,28 @@
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ethernet-phy@0 {
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ethernet-phy@0 {
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linux,phandle = <2452000>;
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linux,phandle = <2452000>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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interrupts = <a 0>;
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interrupts = <3a 0>;
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reg = <0>;
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reg = <0>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@1 {
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ethernet-phy@1 {
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linux,phandle = <2452001>;
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linux,phandle = <2452001>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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interrupts = <a 0>;
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interrupts = <3a 0>;
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reg = <1>;
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reg = <1>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@2 {
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ethernet-phy@2 {
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linux,phandle = <2452002>;
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linux,phandle = <2452002>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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interrupts = <a 0>;
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interrupts = <3a 0>;
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reg = <2>;
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reg = <2>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@3 {
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ethernet-phy@3 {
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linux,phandle = <2452003>;
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linux,phandle = <2452003>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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interrupts = <a 0>;
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interrupts = <3a 0>;
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reg = <3>;
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reg = <3>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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@ -176,8 +176,8 @@
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serial@4500 {
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serial@4500 {
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device_type = "serial";
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device_type = "serial";
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compatible = "ns16550";
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compatible = "ns16550";
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reg = <4500 100>; // reg base, size
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reg = <4500 100>;
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clock-frequency = <0>; // should we fill in in uboot?
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clock-frequency = <0>;
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interrupts = <2a 3>;
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interrupts = <2a 3>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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};
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};
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@ -185,12 +185,120 @@
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serial@4600 {
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serial@4600 {
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device_type = "serial";
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device_type = "serial";
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compatible = "ns16550";
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compatible = "ns16550";
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reg = <4600 100>; // reg base, size
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reg = <4600 100>;
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clock-frequency = <0>; // should we fill in in uboot?
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clock-frequency = <0>;
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interrupts = <2a 3>;
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interrupts = <2a 3>;
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interrupt-parent = <40000>;
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interrupt-parent = <40000>;
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};
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};
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pci@8000 {
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compatible = "86xx";
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device_type = "pci";
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linux,phandle = <8000>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8000 1000>;
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bus-range = <0 fe>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <40000>;
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interrupts = <8 0>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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8800 0 0 1 40000 3 0
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8800 0 0 2 40000 4 0
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8800 0 0 3 40000 5 0
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8800 0 0 4 40000 6 0
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/* IDSEL 0x12 */
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9000 0 0 1 40000 4 0
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9000 0 0 2 40000 5 0
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9000 0 0 3 40000 6 0
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9000 0 0 4 40000 3 0
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/* IDSEL 0x13 */
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9800 0 0 1 40000 5 0
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9800 0 0 2 40000 6 0
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9800 0 0 3 40000 3 0
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9800 0 0 4 40000 4 0
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/* IDSEL 0x14 */
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a000 0 0 1 40000 6 0
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a000 0 0 2 40000 3 0
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a000 0 0 3 40000 4 0
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a000 0 0 4 40000 5 0
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/* IDSEL 0x15 */
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a800 0 0 1 40000 0 0
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a800 0 0 2 40000 0 0
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a800 0 0 3 40000 0 0
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a800 0 0 4 40000 0 0
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/* IDSEL 0x16 */
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b000 0 0 1 40000 0 0
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b000 0 0 2 40000 0 0
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b000 0 0 3 40000 0 0
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b000 0 0 4 40000 0 0
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/* IDSEL 0x17 */
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b800 0 0 1 40000 0 0
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b800 0 0 2 40000 0 0
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b800 0 0 3 40000 0 0
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b800 0 0 4 40000 0 0
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/* IDSEL 0x18 */
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c000 0 0 1 40000 0 0
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c000 0 0 2 40000 0 0
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c000 0 0 3 40000 0 0
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c000 0 0 4 40000 0 0
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/* IDSEL 0x19 */
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c800 0 0 1 40000 0 0
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c800 0 0 2 40000 0 0
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c800 0 0 3 40000 0 0
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c800 0 0 4 40000 0 0
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/* IDSEL 0x1a */
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d000 0 0 1 40000 0 0
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d000 0 0 2 40000 0 0
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d000 0 0 3 40000 0 0
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d000 0 0 4 40000 0 0
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/* IDSEL 0x1b */
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d800 0 0 1 40000 0 0
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d800 0 0 2 40000 0 0
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d800 0 0 3 40000 0 0
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d800 0 0 4 40000 0 0
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/* IDSEL 0x1c */
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e000 0 0 1 40000 0 0
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e000 0 0 2 40000 0 0
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e000 0 0 3 40000 0 0
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e000 0 0 4 40000 0 0
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/* IDSEL 0x1d */
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e800 0 0 1 40000 0 0
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e800 0 0 2 40000 0 0
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e800 0 0 3 40000 0 0
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e800 0 0 4 40000 0 0
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/* IDSEL 0x1e */
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f000 0 0 1 40000 0 0
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f000 0 0 2 40000 0 0
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f000 0 0 3 40000 0 0
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f000 0 0 4 40000 0 0
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/* IDSEL 0x1f */
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f800 0 0 1 40000 6 0
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f800 0 0 2 40000 6 0
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f800 0 0 3 40000 6 0
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f800 0 0 4 40000 6 0
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>;
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};
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pic@40000 {
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pic@40000 {
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linux,phandle = <40000>;
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linux,phandle = <40000>;
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clock-frequency = <0>;
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clock-frequency = <0>;
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@ -83,7 +83,7 @@ U_BOOT_CMD(
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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U_BOOT_CMD(
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U_BOOT_CMD(
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reset, 1, 0, do_reset,
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reset, CFG_MAXARGS, 1, do_reset,
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"reset - Perform RESET of the CPU\n",
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"reset - Perform RESET of the CPU\n",
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NULL
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NULL
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);
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);
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123
doc/README.mpc8641hpcn
Normal file
123
doc/README.mpc8641hpcn
Normal file
@ -0,0 +1,123 @@
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Freescale MPC8641HPCN board
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===========================
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Created 05/24/2006 Haiying Wang
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-------------------------------
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1. Building U-Boot
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------------------
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The 86xx HPCN code base is known to compile using:
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Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
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$ make MPC8641HPCN_config
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Configuring for MPC8641HPCN board...
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$ make
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2. Switch and Jumper Setting
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----------------------------
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Jumpers:
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J14 Pins 1-2 (near plcc32 socket)
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Switches:
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SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
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01100 :: CORE = 2.5:1
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10000 :: CORE = 3:1
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11100 :: CORE = 3.5:1
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10100 :: CORE = 4:1
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01110 :: CORE = 4.5:1
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SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
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001 :: SYSCLK = 40MHz
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SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
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0100 :: 4X
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0110 :: 6X
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1000 :: 8X
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1010 :: 10X
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1100 :: 12X
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1110 :: 14X
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0000 :: 16X
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SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
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SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
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0100000 :: VCORE = 1.11V
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SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
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1 :: VCC_PLAT = 1.0V
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SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
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SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
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SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
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SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
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0 :: boot from PromJet
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SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
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halves (virtual banks)
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0 :: normal
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SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
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SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
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1:1 for PD6
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SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
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SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
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SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
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SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
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SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
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SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
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SW6(7) = 1 CFG_MEMDEBUG = 1 ::
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SW6(8) = 1 CFG_DDRDEBUG = 1 ::
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SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
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SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
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SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
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SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
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SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
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SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
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SW8(7) = 1 ACPWR = 1 :: non-battery
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SW8(8) = 0 CFG_IDWP = 0 :: write enable
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|
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|
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|
3. Flash U-Boot
|
||||||
|
---------------
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|
The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
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|
It is possible to use either half to boot using u-boot. Switch 5 bit 2
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|
is used for this purpose.
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|
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0xFF800000 to 0xFFBFFFFF - 4MB
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0xFFC00000 to 0xFFFFFFFF - 4MB
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When this bit is 0, U-Boot is at 0xFFF00000.
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|
When this bit is 1, U-Boot is at 0xFFB00000.
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|
|
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|
Use the above mentioned flash commands to program the other half, and
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|
use switch 5, bit 2 to alternate between the halves. Note: The booting
|
||||||
|
version of U-Boot will always be at 0xFFF00000.
|
||||||
|
|
||||||
|
To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
|
||||||
|
|
||||||
|
tftp 1000000 u-boot.bin
|
||||||
|
protect off all
|
||||||
|
erase fff00000 ffffffff
|
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|
cp.b 1000000 fff00100 80000
|
||||||
|
|
||||||
|
To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
|
||||||
|
|
||||||
|
tftp 1000000 u-boot.bin
|
||||||
|
erase ffb00000 ffbfffff
|
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|
cp.b 1000000 ffb00100 80000
|
||||||
|
|
||||||
|
|
||||||
|
4. Memory Map
|
||||||
|
-------------
|
||||||
|
|
||||||
|
Memory Range Device Size
|
||||||
|
------------ ------ ----
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||||||
|
0x0000_0000 0x7fff_ffff DDR 2G
|
||||||
|
0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
|
||||||
|
0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
|
||||||
|
0xf800_0000 0xf80f_ffff CCSR 1M
|
||||||
|
0xf810_0000 0xf81f_ffff PIXIS 1M
|
||||||
|
0xf840_0000 0xf840_3fff Stack space 32K
|
||||||
|
0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M
|
||||||
|
0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M
|
||||||
|
0xfe00_0000 0xfeff_ffff Flash(alternate)16M
|
||||||
|
0xff00_0000 0xffff_ffff Flash(boot bank)16M
|
||||||
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