random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-17 22:28:17 +01:00
Code Issues Packages Projects Releases Wiki Activity

Convert CONFIG_VSC7385_ENET et al to Kconfig

Browse Source 
This converts the following to Kconfig:
   CONFIG_VSC7385_ENET
   CONFIG_VSC9953

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-11-19 18:45:39 -05:00
parent a9c3bce362
commit be3bea2ba3
25 changed files with 27 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
configs/MPC837XERDB_defconfig
View File

@ -206,6 +206,7 @@ CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y CONFIG_DM_ETH_PHY=y
CONFIG_RGMII=y CONFIG_RGMII=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_RTC_DS1374=y CONFIG_RTC_DS1374=y
CONFIG_SYS_NS16550_SERIAL=y CONFIG_SYS_NS16550_SERIAL=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -139,6 +139,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -121,6 +121,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_36BIT_defconfig
View File

@ -101,6 +101,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_NAND_defconfig
View File

@ -138,6 +138,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_SDCARD_defconfig
View File

@ -120,6 +120,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View File

@ -122,6 +122,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PC_defconfig
View File

@ -100,6 +100,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PD_NAND_defconfig
View File

@ -141,6 +141,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P1020RDB-PD_defconfig
View File

@ -103,6 +103,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -144,6 +144,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -126,6 +126,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -128,6 +128,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_36BIT_defconfig
View File

@ -106,6 +106,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_NAND_defconfig
View File

@ -143,6 +143,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_SDCARD_defconfig
View File

@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View File

@ -127,6 +127,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

1
configs/P2020RDB-PC_defconfig
View File

@ -105,6 +105,7 @@ CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y CONFIG_PHY_GIGE=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_VSC7385_ENET=y
CONFIG_TSEC_ENET=y CONFIG_TSEC_ENET=y
CONFIG_PCIE_FSL=y CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y CONFIG_DM_RTC=y

6
drivers/net/Kconfig
View File

@ -676,6 +676,12 @@ config XILINX_AXIMRMAC
rates from 10GE to 100GE. This could be present in some of the Xilinx rates from 10GE to 100GE. This could be present in some of the Xilinx
Versal designs. Versal designs.
config VSC7385_ENET
bool "Vitesse 7385 Switch Firmware Upload driver"
config VSC9953
bool "Vitesse VSC9953 L2 Switch driver"
config XILINX_EMACLITE config XILINX_EMACLITE
select PHYLIB select PHYLIB
select MII select MII

5
include/configs/MPC837XERDB.h
View File

@ -14,11 +14,6 @@
* High Level Configuration Options * High Level Configuration Options
*/ */
/*
* On-board devices
*/
#define CONFIG_VSC7385_ENET
/* System performance - define the value i.e. CONFIG_SYS_XXX /* System performance - define the value i.e. CONFIG_SYS_XXX
*/ */

1
include/configs/T104xRDB.h
View File

@ -385,7 +385,6 @@
/* Enable VSC9953 L2 Switch driver on T1040 SoC */ /* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB #ifdef CONFIG_TARGET_T1040RDB
#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08

3
include/configs/p1_p2_rdb_pc.h
View File

@ -13,7 +13,6 @@
#include <linux/stringify.h> #include <linux/stringify.h>
#if defined(CONFIG_TARGET_P1020RDB_PC) #if defined(CONFIG_TARGET_P1020RDB_PC)
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC #define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03 #define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0x5c #define __SW_BOOT_NOR 0x5c
@ -43,7 +42,6 @@
* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
*/ */
#if defined(CONFIG_TARGET_P1020RDB_PD) #if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC #define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03 #define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0x64 #define __SW_BOOT_NOR 0x64
@ -63,7 +61,6 @@
#endif #endif
#if defined(CONFIG_TARGET_P2020RDB) #if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03 #define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28 #define __SW_BOOT_SPI 0x28