random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-11-17 09:18:53 +00:00
Code Issues Packages Projects Releases Wiki Activity

andes: csr.h: Clean up CSR definition

Browse Source 
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
This commit is contained in:
Leo Yu-Chi Liang 2023-12-26 14:17:32 +08:00
parent 670db88c79
commit c36eb2f917
2 changed files with 8 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/riscv/include/asm/arch-andes/csr.h
View File

@ -12,20 +12,16 @@
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc
#define MCACHE_CTL_IC_EN_OFFSET 0
#define MCACHE_CTL_DC_EN_OFFSET 1
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_DC_COHEN_OFFSET 19
#define MCACHE_CTL_DC_COHSTA_OFFSET 20
/* mcache_ctl register */
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
#define CCTL_L1D_WBINVAL_ALL 6

1
arch/riscv/include/asm/csr.h
View File

@ -142,6 +142,7 @@
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_MARCHID 0xf12
#define CSR_MHARTID 0xf14
#ifndef __ASSEMBLY__