random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 21:06:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

imx: imx8ulp: enable MU0_B clk by default

Browse Source 
Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.

And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.

Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2022-04-06 14:30:15 +08:00 committed by Stefano Babic
parent 509b8e7ba1
commit c628016c12
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-imx/imx8ulp/clock.c
View File

@ -214,6 +214,9 @@ void clock_init_late(void)
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
} }
/* enable MU0_MUB clock before access the register of MU0_MUB */
pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
/* /*
* Enable clock division * Enable clock division
* TODO: may not needed after ROM ready. * TODO: may not needed after ROM ready.

3
arch/arm/mach-imx/imx8ulp/soc.c
View File

@ -156,9 +156,6 @@ int m33_image_handshake(ulong timeout_ms)
int ret; int ret;
ulong timeout_us = timeout_ms * 1000; ulong timeout_us = timeout_ms * 1000;
/* enable MU0_MUB clock before access the register of MU0_MUB */
pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */ /* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */ setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */