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Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_FSL_MAX_NUM_OF_SEC

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-07-31 21:08:26 -04:00
parent 7ae1e6a3a3
commit c6eec0182a
9 changed files with 5 additions and 22 deletions
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11
arch/arm/include/asm/arch-fsl-layerscape/config.h
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@ -94,8 +94,6 @@
#define EPU_EPCTR5 0x700060a14ULL #define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL #define EPU_EPGCR 0x700060000ULL
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1088A) #elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
@ -129,7 +127,6 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ /* DCFG - GUR */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
@ -165,8 +162,6 @@
/* DCFG - GUR */ /* DCFG - GUR */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1028A) #elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
@ -204,7 +199,6 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* SEC */ /* SEC */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
/* DCFG - GUR */ /* DCFG - GUR */
@ -258,12 +252,9 @@
#define GIC_ADDR_BIT 31 #define GIC_ADDR_BIT 31
#define SCFG_GIC400_ALIGN 0x1570188 #define SCFG_GIC400_ALIGN 0x1570188
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1012A) #elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000 #define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000 #define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@ -281,8 +272,6 @@
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x01410000 #define GICD_BASE 0x01410000
#define GICC_BASE 0x01420000 #define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else #else
#error SoC not defined #error SoC not defined
#endif #endif

1
arch/arm/include/asm/arch-imx8/imx-regs.h
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@ -48,6 +48,5 @@
#define USB_PHY0_BASE_ADDR 0x5b100000 #define USB_PHY0_BASE_ADDR 0x5b100000
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif /* __ASM_ARCH_IMX8_REGS_H__ */ #endif /* __ASM_ARCH_IMX8_REGS_H__ */

1
arch/arm/include/asm/arch-imx8m/imx-regs.h
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@ -92,7 +92,6 @@
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET) CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !defined(__ASSEMBLY__) #if !defined(__ASSEMBLY__)
#include <asm/types.h> #include <asm/types.h>
#include <linux/bitops.h> #include <linux/bitops.h>

1
arch/arm/include/asm/arch-ls102xa/config.h
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@ -82,7 +82,6 @@
#define DCU_LAYER_MAX_NUM 16 #define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A #ifdef CONFIG_ARCH_LS1021A
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else #else
#error SoC not defined #error SoC not defined
#endif #endif

1
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -244,7 +244,6 @@
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET) CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)

1
arch/arm/include/asm/arch-mx7/imx-regs.h
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@ -221,7 +221,6 @@
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET) CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h> #include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h> #include <asm/types.h>

1
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
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@ -234,7 +234,6 @@
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET) CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))

5
arch/powerpc/include/asm/config_mpc85xx.h
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@ -286,13 +286,8 @@
#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1 #define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif #endif
#if !defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */ #endif /* _ASM_MPC85xx_CONFIG_H_ */

5
drivers/crypto/fsl/Kconfig
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@ -10,6 +10,11 @@ config FSL_CAAM
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM. Job Ring as interface to communicate with CAAM.
config SYS_FSL_MAX_NUM_OF_SEC
int "Number of job rings in the CAAM"
depends on FSL_CAAM
default 1
config CAAM_64BIT config CAAM_64BIT
bool bool
default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8