Merge branch '2021-09-30-whitespace-cleanups' into next

- A large number of whitespace cleanups from Wolfgang

README

@@ -300,7 +300,6 @@ board_init_r():
 	- loads U-Boot or (in falcon mode) Linux
 
 
-
 Configuration Options:
 ----------------------
 

arch/arm/cpu/arm926ejs/cache.c

@@ -89,4 +89,3 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
-

arch/arm/cpu/armv7/psci-common.c

@@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu)
 {
 	return psci_context_id[cpu];
 }
-

arch/arm/cpu/armv8/hisilicon/pinmux.c

@@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
 
 	return 0;
 }
-
-

arch/arm/cpu/armv8/xen/hypercall.S

@@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
 HYPERCALL2(event_channel_op);
 HYPERCALL2(hvm_op);
 HYPERCALL2(memory_op);
-

arch/arm/dts/sama7g5-pinfunc.h

@@ -921,4 +921,3 @@
 #define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 3, 3)
 #define PIN_PE7__ISC_D11		PINMUX_PIN(PIN_PE7, 5, 2)
 #define PIN_PE7__G1_TSUCOMP		PINMUX_PIN(PIN_PE7, 7, 1)
-

arch/arm/include/asm/arch-imxrt/imxrt.h

@@ -8,4 +8,3 @@
 #define _ASM_ARCH_IMXRT_H
 
 #endif /* _ASM_ARCH_IMXRT_H */
-

arch/arm/include/asm/arch-rockchip/f_rockusb.h

@@ -133,4 +133,3 @@ struct f_rockusb {
 /* init rockusb device, tell rockusb which device you want to read/write*/
 void rockusb_dev_init(char *dev_type, int dev_index);
 #endif /* _F_ROCKUSB_H_ */
-

arch/arm/include/asm/arch-stm32/stm32f.h

@@ -18,4 +18,3 @@
 void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_STM32F_H */
-

arch/arm/include/asm/arch-stv0991/stv0991_defs.h

@@ -12,4 +12,3 @@ extern int stv0991_pinmux_config(enum periph_id);
 extern int clock_setup(enum periph_clock);
 
 #endif
-

arch/arm/include/asm/xen.h

@@ -4,4 +4,3 @@
  */
 
 extern unsigned long rom_pointer[];
-

arch/arm/lib/ccn504.S

@@ -78,4 +78,3 @@ ENTRY(ccn504_set_aux)
 
 	ret
 ENDPROC(ccn504_set_aux)
-

arch/arm/mach-at91/armv7/sama7g5_devices.c

@@ -8,4 +8,3 @@ char *get_cpu_name(void)
 {
 	return "SAMA7G5";
 }
-

arch/arm/mach-at91/atmel_sfr.c

@@ -39,4 +39,3 @@ void configure_ddrcfg_input_buffers(bool open)
 	else
 		writel(0, &sfr->ddrcfg);
 }
-

arch/arm/mach-bcm283x/msg.c

@@ -196,4 +196,3 @@ int bcm2711_notify_vl805_reset(void)
 
 	return 0;
 }
-

arch/arm/mach-imx/mx7/soc.c

@@ -445,4 +445,3 @@ void reset_misc(void)
 #endif
 #endif
 }
-

arch/arm/mach-kirkwood/cpu.c

@@ -278,4 +278,3 @@ int cpu_eth_init(struct bd_info *bis)
 	return 0;
 }
 #endif
-

arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c

@@ -14,8 +14,6 @@
 #include "sys_env_lib.h"
 #include "ctrl_pex.h"
 
-
-
 /*
  * serdes_seq_db - holds all serdes sequences, their size and the
  * relevant index in the data array initialized in serdes_seq_init

arch/arm/mach-octeontx/Makefile

@@ -6,4 +6,3 @@
 # */
 
 obj-y += lowlevel_init.o clock.o cpu.o
-

arch/arm/mach-octeontx2/Makefile

@@ -6,4 +6,3 @@
 # */
 
 obj-y += lowlevel_init.o clock.o cpu.o
-

arch/arm/mach-omap2/pipe3-phy.c

@@ -229,4 +229,3 @@ int phy_pipe3_power_off(struct omap_pipe3 *phy)
 
 	return 0;
 }
-

arch/arm/mach-snapdragon/dram.c

@@ -97,4 +97,3 @@ int msm_fixup_memory(void *blob)
 
 	return 0;
 }
-

arch/arm/mach-tegra/tegra20/display.c

@@ -12,4 +12,3 @@
 #include <asm/arch-tegra/dc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
-

arch/arm/mach-versatile/timer.c

@@ -60,4 +60,3 @@ int timer_init (void)
 
 	return 0;
 }
-

arch/m68k/cpu/mcf530x/Makefile

@@ -4,4 +4,3 @@
 
 extra-y	= start.o
 obj-y	= interrupts.o cpu.o speed.o cpu_init.o
-

arch/m68k/include/asm/immap_5307.h

@@ -114,4 +114,3 @@ typedef struct gpio {
 } gpio_t;
 
 #endif				/* __IMMAP_5307__ */
-

arch/m68k/include/asm/m5307.h

@@ -66,4 +66,3 @@
 #define	MCFSIM_ICR_PRI3		0x03	/* Priority 3 intr */
 
 #endif	/* mcf5307_h */
-

arch/mips/mach-jz47xx/include/mach/jz4780_dram.h

@@ -454,4 +454,3 @@ void pll_init(void);
 void sdram_init(void);
 
 #endif	/* __JZ4780_DRAM_H__ */
-

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -399,4 +399,3 @@ const char *serdes_clock_to_string(u32 clock)
 #endif
 	}
 }
-

arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -885,4 +885,3 @@ const char *serdes_clock_to_string(u32 clock)
 		return "150";
 	}
 }
-

arch/powerpc/lib/ppccache.S

@@ -104,4 +104,3 @@ _GLOBAL(invalidate_dcache_range)
 	sync				/* wait for dcbi's to get to ram */
 #endif
 	blr
-

arch/sh/lib/time.c

@@ -32,4 +32,3 @@ int timer_init(void)
 
 	return 0;
 }
-

arch/xtensa/include/asm/arch-dc232b/core.h

@@ -127,8 +127,6 @@
 #define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
@@ -419,4 +417,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

arch/xtensa/include/asm/arch-dc232b/tie-asm.h

@@ -26,7 +26,6 @@
 #define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
 
 
-
 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
  * (not including zero-overhead loop registers).
  * Save area ptr (clobbered):  ptr  (1 byte aligned)
@@ -109,12 +108,8 @@
 	.endif
 	.endm	// xchal_ncp_load
 
-
-
 #define XCHAL_NCP_NUM_ATMPS	2
 
-
 #define XCHAL_SA_NUM_ATMPS	2
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

arch/xtensa/include/asm/arch-dc232b/tie.h

@@ -126,4 +126,3 @@
 #define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

arch/xtensa/include/asm/arch-dc233c/core.h

@@ -149,13 +149,10 @@
 #define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
 
-
 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 
 /*----------------------------------------------------------------------
@@ -450,4 +447,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

arch/xtensa/include/asm/arch-dc233c/tie-asm.h

@@ -31,8 +31,6 @@
 					| ((ccuse) & XTHAL_SAS_ANYCC)  \
 					| ((abi)   & XTHAL_SAS_ANYABI) )
 
-
-
     /*
      *  Macro to save all non-coprocessor (extra) custom TIE and optional state
      *  (not including zero-overhead loop registers).
@@ -164,9 +162,6 @@
 
 #define XCHAL_NCP_NUM_ATMPS	1
 
-
-
 #define XCHAL_SA_NUM_ATMPS	1
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

arch/xtensa/include/asm/arch-dc233c/tie.h

@@ -126,4 +126,3 @@
 #define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

arch/xtensa/include/asm/arch-de212/core.h

@@ -206,13 +206,10 @@
 #define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
 
-
 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 
 /*----------------------------------------------------------------------
@@ -569,4 +566,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

arch/xtensa/include/asm/arch-de212/tie-asm.h

@@ -146,4 +146,3 @@
 #define XCHAL_SA_NUM_ATMPS	1
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

arch/xtensa/include/asm/arch-de212/tie.h

@@ -112,4 +112,3 @@
 	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

arch/xtensa/include/asm/cacheasm.h

@@ -134,7 +134,6 @@
 	.endm
 
 
-
 	.macro	___flush_invalidate_dcache_range ar as at
 
 #if XCHAL_DCACHE_SIZE
@@ -171,7 +170,6 @@
 	.endm
 
 
-
 	.macro	___flush_invalidate_dcache_page ar as
 
 #if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/regs.h

@@ -91,4 +91,3 @@
 #define DEBUGCAUSE_ICOUNT_BIT		0	/* ICOUNT would incr. to zero */
 
 #endif /* _XTENSA_SPECREG_H */
-

arch/xtensa/lib/relocate.c

@@ -14,4 +14,3 @@ int clear_bss(void)
 	memset((void *)&__bss_start, 0x00, len);
 	return 0;
 }
-

board/Marvell/octeontx/smc.c

@@ -22,4 +22,3 @@ ssize_t smc_dram_size(unsigned int node)
 
 	return regs.regs[0];
 }
-

board/Marvell/octeontx2/soc-utils.c

@@ -46,4 +46,3 @@ const char *read_board_name(void)
 {
 	return fdt_get_board_model();
 }
-

board/atmark-techno/armadillo-800eva/Makefile

@@ -3,4 +3,3 @@
 # Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 
 obj-y	+= armadillo-800eva.o
-

board/atmel/sama7g5ek/sama7g5ek.c

@@ -74,4 +74,3 @@ int dram_init(void)
 				    CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
-

board/beacon/imx8mn/README

@@ -36,4 +36,3 @@ Boot
 ====
 Set baseboard DIP switch:
 S17: 1100XXXX
-

board/beacon/imx8mn/lpddr4_timing.c

@@ -1431,4 +1431,3 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 400, 100, },
 };
-

board/boundary/nitrogen6x/README.mx6qsabrelite

@@ -116,4 +116,3 @@ Note: This will upload and run the U-Boot image in memory, the SPI will not be
 5. Use one of previous descriptions to re-flash the SPI-NOR as required.
 
 6. Ensure SW1 is returned to "00" to boot from the fuses once done.
-

board/cadence/xtfpga/README

@@ -122,4 +122,3 @@ variable to make.
 Because this problem is easy to fall into and difficult to debug
 if one doesn't expect it, the linker script provides a link-time
 check and fatal error message if the image size exceeds 128 KB.
-

board/compulab/cm_t43/spl.c

@@ -133,4 +133,3 @@ void sdram_init(void)
 
 	hang();
 }
-

board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c

@@ -1845,4 +1845,3 @@ struct dram_timing_info ucm_dram_timing_01061010 = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 2400, 400, 100, },
 };
-

board/freescale/common/zm7300.c

@@ -230,4 +230,3 @@ int zm_enable_wp()
 	}
 	return 0;
 }
-

board/freescale/imx8mn_evk/ddr4_timing.c

@@ -1052,4 +1052,3 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 2400, 1066, },
 };
-

board/freescale/imx8mn_evk/ddr4_timing_ld.c

@@ -1054,4 +1054,3 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 1600, 1066, },
 };
-

board/freescale/ls1088a/ddr.c

@@ -88,8 +88,6 @@ found:
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
 
-
-
 	popts->half_strength_driver_enable = 0;
 	/*
 	 * Write leveling override

board/freescale/ls2080aqds/README

@@ -213,4 +213,3 @@ DPMAC13 -> PHY4-P0
 DPMAC14 -> PHY4-P1
 DPMAC15 -> PHY4-P2
 DPMAC16 -> PHY4-P3
-

board/freescale/ls2080ardb/README

@@ -132,4 +132,3 @@ below:
 => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
    earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
    hugepages=16 mem=2048M'
-

board/freescale/mx6memcal/mx6memcal.c

@@ -30,4 +30,3 @@ int dram_init(void)
 	gd->ram_size = imx_ddr_size();
 	return 0;
 }
-

board/freescale/t208xqds/README

@@ -158,7 +158,6 @@ Start Address   End Address	Definition			Max size
 0xE8000000	0xE801FFFF	RCW (current bank)		128KB
 
 
-
 Software configurations and board settings
 ------------------------------------------
 1. NOR boot:

board/freescale/t4rdb/cpld.h

@@ -45,4 +45,3 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
 #define CPLD_WRITE(reg, value) \
 		cpld_write(offsetof(struct cpld_data, reg), value)
-

board/gateworks/gw_ventana/Makefile

@@ -8,4 +8,3 @@
 
 obj-y  := gw_ventana.o gsc.o eeprom.o common.o
 obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
-

board/gateworks/gw_ventana/gsc.h

@@ -69,4 +69,3 @@ int gsc_info(int verbose);
 int gsc_boot_wd_disable(void);
 const char *gsc_get_dtb_name(int level, char *buf, int sz);
 #endif
-

board/gdsys/a38x/dt_helpers.c

@@ -39,4 +39,3 @@ int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
 
 	return dm_gpio_request(gpio, gpio_name);
 }
-

board/ge/common/ge_rtc.c

@@ -53,4 +53,3 @@ void check_time(void)
 	else
 		env_set("rtc_status", "OK");
 }
-

board/ge/mx53ppd/mx53ppd_video.c

@@ -92,4 +92,3 @@ struct display_info_t const displays[] = {
 };
 
 size_t display_count = ARRAY_SIZE(displays);
-

board/hisilicon/poplar/poplar.c

@@ -195,4 +195,3 @@ int board_init(void)
 
 	return 0;
 }
-

board/keymile/common/qrio.c

@@ -290,4 +290,3 @@ int get_scl(void)
 	return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
 			     KM_I2C_DEBLOCK_SCL);
 }
-

board/logicpd/imx6/Makefile

@@ -7,4 +7,3 @@
 #
 
 obj-y  := imx6logic.o
-

board/logicpd/imx6/README

@@ -80,4 +80,3 @@ while starting.
 
 Additional Support Documentation can be found at:
 https://support.logicpd.com/
-

board/mediatek/mt7622/Makefile

@@ -1,4 +1,3 @@
 # SPDX-License-Identifier:	GPL-2.0
 
 obj-y	+= mt7622_rfb.o
-

board/mqmaker/miqi_rk3288/miqi-rk3288.c

@@ -2,4 +2,3 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  */
-

board/mscc/jr2/Makefile

@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 obj-$(CONFIG_SOC_JR2)	:= jr2.o
-

board/mscc/ocelot/Makefile

@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 obj-$(CONFIG_SOC_OCELOT)	:= ocelot.o
-

board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c

@@ -289,4 +289,3 @@ int ps7_init(void)
 		return ret;
 	return PS7_INIT_SUCCESS;
 }
-

board/phytium/durian/Makefile

@@ -6,4 +6,3 @@
 #
 
 obj-y += durian.o
-

board/phytium/durian/cpu.h

@@ -20,4 +20,3 @@
 #define HNF_BASE            (unsigned long)(0x3A200000)
 
 #endif /* _FT_DURIAN_H */
-

board/phytium/durian/durian.c

@@ -113,4 +113,3 @@ int last_stage_init(void)
 	}
 	return ret;
 }
-

board/rockchip/evb_rk3229/evb_rk3229.c

@@ -7,4 +7,3 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/uart.h>
-

board/rockchip/evb_rk3288/evb-rk3288.c

@@ -2,4 +2,3 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  */
-

board/rockchip/evb_rk3328/evb-rk3328.c

@@ -2,4 +2,3 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  */
-

board/synopsys/axs10x/axs10x.h

@@ -12,4 +12,3 @@ enum {
 };
 
 #endif /* _BOARD_SYNOPSYS_AXS10X_H */
-

board/technexion/pico-imx7d/pico-imx7d.c

@@ -244,4 +244,3 @@ int board_ehci_hcd_init(int port)
 	}
 	return 0;
 }
-

board/technexion/pico-imx8mq/lpddr4_timing_1gb.c

@@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_1gb = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 667, },
 };
-

board/technexion/pico-imx8mq/lpddr4_timing_2gb.c

@@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_2gb = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 667, },
 };
-

board/technexion/pico-imx8mq/lpddr4_timing_3gb.c

@@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_3gb = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 667, },
 };
-

board/technexion/pico-imx8mq/lpddr4_timing_4gb.c

@@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_4gb = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 667, },
 };
-

board/terasic/de0-nano-soc/qts/pll_config.h

@@ -81,4 +81,3 @@
 #define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
 
 #endif /* _PRELOADER_PLL_CONFIG_H_ */
-

board/xen/xenguest_arm64/xenguest_arm64.c

@@ -195,4 +195,3 @@ void board_cleanup_before_linux(void)
 {
 	xen_fini();
 }
-

board/xilinx/versal/cmds.c

@@ -102,4 +102,3 @@ U_BOOT_CMD(versal, 4, 1, do_versal,
 	   "versal sub-system",
 	   versal_help_text
 )
-

board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c

@@ -12399,8 +12399,6 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-
-
 #include "xil_io.h"
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
@@ -12477,15 +12475,9 @@ ps7_init()
   ret = ps7_config (ps7_ddr_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
 
-
-
   // Peripherals init
   ret = ps7_config (ps7_peripherals_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
   //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
   return PS7_INIT_SUCCESS;
 }
-
-
-
-

board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c

@@ -12732,8 +12732,6 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-
-
 #include "xil_io.h"
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
@@ -12810,8 +12808,6 @@ ps7_init()
   ret = ps7_config (ps7_ddr_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
 
-
-
   // Peripherals init
   ret = ps7_config (ps7_peripherals_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;

board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c

@@ -12639,8 +12639,6 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-
-
 #include "xil_io.h"
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
@@ -12717,15 +12715,9 @@ ps7_init()
   ret = ps7_config (ps7_ddr_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
 
-
-
   // Peripherals init
   ret = ps7_config (ps7_peripherals_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
   //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
   return PS7_INIT_SUCCESS;
 }
-
-
-
-

board/xilinx/zynq/zynq-zed/ps7_init_gpl.c

@@ -12297,8 +12297,6 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-
-
 #include "xil_io.h"
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
@@ -12375,15 +12373,9 @@ ps7_init()
   ret = ps7_config (ps7_ddr_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
 
-
-
   // Peripherals init
   ret = ps7_config (ps7_peripherals_init_data);
   if (ret != PS7_INIT_SUCCESS) return ret;
   //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
   return PS7_INIT_SUCCESS;
 }
-
-
-
-

board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c

@@ -12565,4 +12565,3 @@ int ps7_init(void)
 		return ret;
 	return PS7_INIT_SUCCESS;
 }
-

cmd/bedbug.c

@@ -39,7 +39,6 @@ int bedbug_puts (const char *str)
 }				/* bedbug_puts */
 
 
-
 /* ======================================================================
  * Initialize the bug_ctx structure used by the bedbug debugger.  This is
  * specific to the CPU since each has different debug registers and
@@ -53,7 +52,6 @@ int bedbug_init(void)
 }				/* bedbug_init */
 
 
-
 /* ======================================================================
  * Entry point from the interpreter to the disassembler.  Repeated calls
  * will resume from the last disassembled address.
@@ -183,7 +181,6 @@ void do_bedbug_breakpoint (struct pt_regs *regs)
 }				/* do_bedbug_breakpoint */
 
 
-
 /* ======================================================================
  * Called from the CPU-specific breakpoint handling routine.  Enter a
  * mini main loop until the stopped flag is cleared from the breakpoint
@@ -241,7 +238,6 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs)
 }				/* bedbug_main_loop */
 
 
-
 /* ======================================================================
  * Interpreter command to continue from a breakpoint.  Just clears the
  * stopped flag in the context so that the breakpoint routine will

cmd/pvblock.c

@@ -27,4 +27,3 @@ U_BOOT_CMD(pvblock, 5, 1, do_pvblock,
 	   "pvblock write addr blk# cnt - read/write `cnt'"
 	   " blocks starting at block `blk#'\n"
 	   "    to/from memory address `addr'");
-

cmd/scp03.c

@@ -49,4 +49,3 @@ static char text[] =
 U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text,
 	U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable),
 	U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision));
-