mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-02 13:08:16 +00:00
Merge branch '2021-09-30-whitespace-cleanups' into next
- A large number of whitespace cleanups from Wolfgang
This commit is contained in:
Tom Rini
commit
c8988efc88
1
README
1
README
@ -300,7 +300,6 @@ board_init_r():
|
||||
- loads U-Boot or (in falcon mode) Linux
|
||||
|
||||
|
||||
|
||||
Configuration Options:
|
||||
----------------------
|
||||
|
||||
|
||||
@ -89,4 +89,3 @@ void enable_caches(void)
|
||||
dcache_enable();
|
||||
#endif
|
||||
}
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||||
|
||||
|
||||
@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu)
|
||||
{
|
||||
return psci_context_id[cpu];
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}
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||||
|
||||
|
||||
@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
|
||||
|
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return 0;
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}
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||||
|
||||
|
||||
|
||||
@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
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HYPERCALL2(event_channel_op);
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HYPERCALL2(hvm_op);
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HYPERCALL2(memory_op);
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@ -921,4 +921,3 @@
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#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3)
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#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2)
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#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1)
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@ -8,4 +8,3 @@
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#define _ASM_ARCH_IMXRT_H
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#endif /* _ASM_ARCH_IMXRT_H */
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@ -133,4 +133,3 @@ struct f_rockusb {
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/* init rockusb device, tell rockusb which device you want to read/write*/
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void rockusb_dev_init(char *dev_type, int dev_index);
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#endif /* _F_ROCKUSB_H_ */
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@ -18,4 +18,3 @@
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void stm32_flash_latency_cfg(int latency);
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#endif /* _ASM_ARCH_STM32F_H */
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@ -12,4 +12,3 @@ extern int stv0991_pinmux_config(enum periph_id);
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extern int clock_setup(enum periph_clock);
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#endif
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@ -4,4 +4,3 @@
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*/
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extern unsigned long rom_pointer[];
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@ -78,4 +78,3 @@ ENTRY(ccn504_set_aux)
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ret
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ENDPROC(ccn504_set_aux)
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@ -8,4 +8,3 @@ char *get_cpu_name(void)
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{
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return "SAMA7G5";
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}
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@ -39,4 +39,3 @@ void configure_ddrcfg_input_buffers(bool open)
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else
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writel(0, &sfr->ddrcfg);
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}
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@ -196,4 +196,3 @@ int bcm2711_notify_vl805_reset(void)
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return 0;
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}
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@ -445,4 +445,3 @@ void reset_misc(void)
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#endif
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#endif
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}
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@ -278,4 +278,3 @@ int cpu_eth_init(struct bd_info *bis)
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return 0;
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}
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#endif
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@ -14,8 +14,6 @@
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#include "sys_env_lib.h"
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#include "ctrl_pex.h"
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|
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/*
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* serdes_seq_db - holds all serdes sequences, their size and the
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* relevant index in the data array initialized in serdes_seq_init
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@ -6,4 +6,3 @@
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# */
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obj-y += lowlevel_init.o clock.o cpu.o
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@ -6,4 +6,3 @@
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# */
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obj-y += lowlevel_init.o clock.o cpu.o
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@ -229,4 +229,3 @@ int phy_pipe3_power_off(struct omap_pipe3 *phy)
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return 0;
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}
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@ -97,4 +97,3 @@ int msm_fixup_memory(void *blob)
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return 0;
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}
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@ -12,4 +12,3 @@
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#include <asm/arch-tegra/dc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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@ -60,4 +60,3 @@ int timer_init (void)
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return 0;
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}
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@ -4,4 +4,3 @@
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extra-y = start.o
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obj-y = interrupts.o cpu.o speed.o cpu_init.o
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@ -114,4 +114,3 @@ typedef struct gpio {
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} gpio_t;
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#endif /* __IMMAP_5307__ */
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@ -66,4 +66,3 @@
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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||||
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#endif /* mcf5307_h */
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||||
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||||
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@ -454,4 +454,3 @@ void pll_init(void);
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void sdram_init(void);
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|
||||
#endif /* __JZ4780_DRAM_H__ */
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||||
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@ -399,4 +399,3 @@ const char *serdes_clock_to_string(u32 clock)
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#endif
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||||
}
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||||
}
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||||
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@ -885,4 +885,3 @@ const char *serdes_clock_to_string(u32 clock)
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return "150";
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}
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}
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@ -104,4 +104,3 @@ _GLOBAL(invalidate_dcache_range)
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sync /* wait for dcbi's to get to ram */
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#endif
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blr
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@ -32,4 +32,3 @@ int timer_init(void)
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return 0;
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}
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@ -127,8 +127,6 @@
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#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
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||||
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/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
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@ -419,4 +417,3 @@
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||||
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||||
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -26,7 +26,6 @@
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
|
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@ -109,12 +108,8 @@
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||||
.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 2
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|
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#define XCHAL_SA_NUM_ATMPS 2
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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@ -126,4 +126,3 @@
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#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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@ -149,13 +149,10 @@
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#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
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|
||||
|
||||
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/****************************************************************************
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||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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@ -450,4 +447,3 @@
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -31,8 +31,6 @@
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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|
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/*
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* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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@ -164,9 +162,6 @@
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#define XCHAL_NCP_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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@ -126,4 +126,3 @@
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#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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@ -206,13 +206,10 @@
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#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
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****************************************************************************/
|
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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@ -569,4 +566,3 @@
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -146,4 +146,3 @@
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#define XCHAL_SA_NUM_ATMPS 1
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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@ -112,4 +112,3 @@
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3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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@ -134,7 +134,6 @@
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.endm
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|
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.macro ___flush_invalidate_dcache_range ar as at
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|
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#if XCHAL_DCACHE_SIZE
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@ -171,7 +170,6 @@
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.endm
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||||
|
||||
|
||||
|
||||
.macro ___flush_invalidate_dcache_page ar as
|
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|
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#if XCHAL_DCACHE_SIZE
|
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|
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@ -91,4 +91,3 @@
|
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#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
|
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|
||||
#endif /* _XTENSA_SPECREG_H */
|
||||
|
||||
|
||||
@ -14,4 +14,3 @@ int clear_bss(void)
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memset((void *)&__bss_start, 0x00, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -22,4 +22,3 @@ ssize_t smc_dram_size(unsigned int node)
|
||||
|
||||
return regs.regs[0];
|
||||
}
|
||||
|
||||
|
||||
@ -46,4 +46,3 @@ const char *read_board_name(void)
|
||||
{
|
||||
return fdt_get_board_model();
|
||||
}
|
||||
|
||||
|
||||
@ -3,4 +3,3 @@
|
||||
# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
|
||||
obj-y += armadillo-800eva.o
|
||||
|
||||
|
||||
@ -74,4 +74,3 @@ int dram_init(void)
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -36,4 +36,3 @@ Boot
|
||||
====
|
||||
Set baseboard DIP switch:
|
||||
S17: 1100XXXX
|
||||
|
||||
|
||||
@ -1431,4 +1431,3 @@ struct dram_timing_info dram_timing = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3200, 400, 100, },
|
||||
};
|
||||
|
||||
|
||||
@ -116,4 +116,3 @@ Note: This will upload and run the U-Boot image in memory, the SPI will not be
|
||||
5. Use one of previous descriptions to re-flash the SPI-NOR as required.
|
||||
|
||||
6. Ensure SW1 is returned to "00" to boot from the fuses once done.
|
||||
|
||||
|
||||
@ -122,4 +122,3 @@ variable to make.
|
||||
Because this problem is easy to fall into and difficult to debug
|
||||
if one doesn't expect it, the linker script provides a link-time
|
||||
check and fatal error message if the image size exceeds 128 KB.
|
||||
|
||||
|
||||
@ -133,4 +133,3 @@ void sdram_init(void)
|
||||
|
||||
hang();
|
||||
}
|
||||
|
||||
|
||||
@ -1845,4 +1845,3 @@ struct dram_timing_info ucm_dram_timing_01061010 = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 2400, 400, 100, },
|
||||
};
|
||||
|
||||
|
||||
@ -230,4 +230,3 @@ int zm_enable_wp()
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1052,4 +1052,3 @@ struct dram_timing_info dram_timing = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 2400, 1066, },
|
||||
};
|
||||
|
||||
|
||||
@ -1054,4 +1054,3 @@ struct dram_timing_info dram_timing = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 1600, 1066, },
|
||||
};
|
||||
|
||||
|
||||
@ -88,8 +88,6 @@ found:
|
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
|
||||
pbsp->wrlvl_ctl_3);
|
||||
|
||||
|
||||
|
||||
popts->half_strength_driver_enable = 0;
|
||||
/*
|
||||
* Write leveling override
|
||||
|
||||
@ -213,4 +213,3 @@ DPMAC13 -> PHY4-P0
|
||||
DPMAC14 -> PHY4-P1
|
||||
DPMAC15 -> PHY4-P2
|
||||
DPMAC16 -> PHY4-P3
|
||||
|
||||
|
||||
@ -132,4 +132,3 @@ below:
|
||||
=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
|
||||
earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
|
||||
hugepages=16 mem=2048M'
|
||||
|
||||
|
||||
@ -30,4 +30,3 @@ int dram_init(void)
|
||||
gd->ram_size = imx_ddr_size();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -158,7 +158,6 @@ Start Address End Address Definition Max size
|
||||
0xE8000000 0xE801FFFF RCW (current bank) 128KB
|
||||
|
||||
|
||||
|
||||
Software configurations and board settings
|
||||
------------------------------------------
|
||||
1. NOR boot:
|
||||
|
||||
@ -45,4 +45,3 @@ void cpld_write(unsigned int reg, u8 value);
|
||||
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
||||
#define CPLD_WRITE(reg, value) \
|
||||
cpld_write(offsetof(struct cpld_data, reg), value)
|
||||
|
||||
|
||||
@ -8,4 +8,3 @@
|
||||
|
||||
obj-y := gw_ventana.o gsc.o eeprom.o common.o
|
||||
obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
|
||||
|
||||
|
||||
@ -69,4 +69,3 @@ int gsc_info(int verbose);
|
||||
int gsc_boot_wd_disable(void);
|
||||
const char *gsc_get_dtb_name(int level, char *buf, int sz);
|
||||
#endif
|
||||
|
||||
|
||||
@ -39,4 +39,3 @@ int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
|
||||
|
||||
return dm_gpio_request(gpio, gpio_name);
|
||||
}
|
||||
|
||||
|
||||
@ -53,4 +53,3 @@ void check_time(void)
|
||||
else
|
||||
env_set("rtc_status", "OK");
|
||||
}
|
||||
|
||||
|
||||
@ -92,4 +92,3 @@ struct display_info_t const displays[] = {
|
||||
};
|
||||
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
|
||||
|
||||
@ -195,4 +195,3 @@ int board_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -290,4 +290,3 @@ int get_scl(void)
|
||||
return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
|
||||
KM_I2C_DEBLOCK_SCL);
|
||||
}
|
||||
|
||||
|
||||
@ -7,4 +7,3 @@
|
||||
#
|
||||
|
||||
obj-y := imx6logic.o
|
||||
|
||||
|
||||
@ -80,4 +80,3 @@ while starting.
|
||||
|
||||
Additional Support Documentation can be found at:
|
||||
https://support.logicpd.com/
|
||||
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += mt7622_rfb.o
|
||||
|
||||
|
||||
@ -2,4 +2,3 @@
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
obj-$(CONFIG_SOC_JR2) := jr2.o
|
||||
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
obj-$(CONFIG_SOC_OCELOT) := ocelot.o
|
||||
|
||||
|
||||
@ -289,4 +289,3 @@ int ps7_init(void)
|
||||
return ret;
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@ -6,4 +6,3 @@
|
||||
#
|
||||
|
||||
obj-y += durian.o
|
||||
|
||||
|
||||
@ -20,4 +20,3 @@
|
||||
#define HNF_BASE (unsigned long)(0x3A200000)
|
||||
|
||||
#endif /* _FT_DURIAN_H */
|
||||
|
||||
|
||||
@ -113,4 +113,3 @@ int last_stage_init(void)
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -7,4 +7,3 @@
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-rockchip/uart.h>
|
||||
|
||||
|
||||
@ -2,4 +2,3 @@
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
|
||||
@ -2,4 +2,3 @@
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
|
||||
@ -12,4 +12,3 @@ enum {
|
||||
};
|
||||
|
||||
#endif /* _BOARD_SYNOPSYS_AXS10X_H */
|
||||
|
||||
|
||||
@ -244,4 +244,3 @@ int board_ehci_hcd_init(int port)
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_1gb = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3200, 667, },
|
||||
};
|
||||
|
||||
|
||||
@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_2gb = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3200, 667, },
|
||||
};
|
||||
|
||||
|
||||
@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_3gb = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3200, 667, },
|
||||
};
|
||||
|
||||
|
||||
@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_4gb = {
|
||||
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
||||
.fsp_table = { 3200, 667, },
|
||||
};
|
||||
|
||||
|
||||
@ -81,4 +81,3 @@
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
|
||||
|
||||
#endif /* _PRELOADER_PLL_CONFIG_H_ */
|
||||
|
||||
|
||||
@ -195,4 +195,3 @@ void board_cleanup_before_linux(void)
|
||||
{
|
||||
xen_fini();
|
||||
}
|
||||
|
||||
|
||||
@ -102,4 +102,3 @@ U_BOOT_CMD(versal, 4, 1, do_versal,
|
||||
"versal sub-system",
|
||||
versal_help_text
|
||||
)
|
||||
|
||||
|
||||
@ -12399,8 +12399,6 @@ unsigned long ps7_post_config_1_0[] = {
|
||||
//
|
||||
};
|
||||
|
||||
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
@ -12477,15 +12475,9 @@ ps7_init()
|
||||
ret = ps7_config (ps7_ddr_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
|
||||
|
||||
|
||||
// Peripherals init
|
||||
ret = ps7_config (ps7_peripherals_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12732,8 +12732,6 @@ unsigned long ps7_post_config_1_0[] = {
|
||||
//
|
||||
};
|
||||
|
||||
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
@ -12810,8 +12808,6 @@ ps7_init()
|
||||
ret = ps7_config (ps7_ddr_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
|
||||
|
||||
|
||||
// Peripherals init
|
||||
ret = ps7_config (ps7_peripherals_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
|
||||
@ -12639,8 +12639,6 @@ unsigned long ps7_post_config_1_0[] = {
|
||||
//
|
||||
};
|
||||
|
||||
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
@ -12717,15 +12715,9 @@ ps7_init()
|
||||
ret = ps7_config (ps7_ddr_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
|
||||
|
||||
|
||||
// Peripherals init
|
||||
ret = ps7_config (ps7_peripherals_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12297,8 +12297,6 @@ unsigned long ps7_post_config_1_0[] = {
|
||||
//
|
||||
};
|
||||
|
||||
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
|
||||
@ -12375,15 +12373,9 @@ ps7_init()
|
||||
ret = ps7_config (ps7_ddr_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
|
||||
|
||||
|
||||
// Peripherals init
|
||||
ret = ps7_config (ps7_peripherals_init_data);
|
||||
if (ret != PS7_INIT_SUCCESS) return ret;
|
||||
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12565,4 +12565,3 @@ int ps7_init(void)
|
||||
return ret;
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@ -39,7 +39,6 @@ int bedbug_puts (const char *str)
|
||||
} /* bedbug_puts */
|
||||
|
||||
|
||||
|
||||
/* ======================================================================
|
||||
* Initialize the bug_ctx structure used by the bedbug debugger. This is
|
||||
* specific to the CPU since each has different debug registers and
|
||||
@ -53,7 +52,6 @@ int bedbug_init(void)
|
||||
} /* bedbug_init */
|
||||
|
||||
|
||||
|
||||
/* ======================================================================
|
||||
* Entry point from the interpreter to the disassembler. Repeated calls
|
||||
* will resume from the last disassembled address.
|
||||
@ -183,7 +181,6 @@ void do_bedbug_breakpoint (struct pt_regs *regs)
|
||||
} /* do_bedbug_breakpoint */
|
||||
|
||||
|
||||
|
||||
/* ======================================================================
|
||||
* Called from the CPU-specific breakpoint handling routine. Enter a
|
||||
* mini main loop until the stopped flag is cleared from the breakpoint
|
||||
@ -241,7 +238,6 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs)
|
||||
} /* bedbug_main_loop */
|
||||
|
||||
|
||||
|
||||
/* ======================================================================
|
||||
* Interpreter command to continue from a breakpoint. Just clears the
|
||||
* stopped flag in the context so that the breakpoint routine will
|
||||
|
||||
@ -27,4 +27,3 @@ U_BOOT_CMD(pvblock, 5, 1, do_pvblock,
|
||||
"pvblock write addr blk# cnt - read/write `cnt'"
|
||||
" blocks starting at block `blk#'\n"
|
||||
" to/from memory address `addr'");
|
||||
|
||||
|
||||
@ -49,4 +49,3 @@ static char text[] =
|
||||
U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text,
|
||||
U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable),
|
||||
U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision));
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user