random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 04:46:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

ti: keystone: Clean up or migrate some NAND related options.

Browse Source 
The COFNIG_KEYSTONE_RBL_NAND option is always enabled for the driver on
keystone platforms, but not older davinci platforms.  Use def_bool for
the symbol. For CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE, it's only used within
the driver and derived from another symbol, so remove CONFIG from the
name.  Finally, CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE is a bit more fixed.
For now, use the value directly.  Long term, as part of DM'ifying NAND,
this should come from the device tree.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-09-12 20:32:24 -04:00
parent bdeedc16e1
commit c8c934b910
3 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/mtd/nand/raw/Kconfig
View File

@ -105,6 +105,10 @@ config NAND_DAVINCI
Enable this driver for NAND flash controllers available in TI Davinci Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms and Keystone2 platforms
config KEYSTONE_RBL_NAND
depends on ARCH_KEYSTONE
def_bool y
config NAND_DENALI config NAND_DENALI
bool bool
select SYS_NAND_SELF_INIT select SYS_NAND_SELF_INIT

12
drivers/mtd/nand/raw/davinci_nand.c
View File

@ -347,9 +347,9 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
}; };
#ifdef CONFIG_SYS_NAND_PAGE_2K #ifdef CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11)
#elif defined(CONFIG_SYS_NAND_PAGE_4K) #elif defined(CONFIG_SYS_NAND_PAGE_4K)
#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 #define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12)
#endif #endif
/** /**
@ -371,7 +371,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
struct nand_ecclayout *saved_ecc_layout; struct nand_ecclayout *saved_ecc_layout;
/* save current ECC layout and assign Keystone RBL ECC layout */ /* save current ECC layout and assign Keystone RBL ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
saved_ecc_layout = chip->ecc.layout; saved_ecc_layout = chip->ecc.layout;
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail; mtd->oobavail = chip->ecc.layout->oobavail;
@ -402,7 +402,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
err: err:
/* restore ECC layout */ /* restore ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout; chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail; mtd->oobavail = saved_ecc_layout->oobavail;
} }
@ -433,7 +433,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *
struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
/* save current ECC layout and assign Keystone RBL ECC layout */ /* save current ECC layout and assign Keystone RBL ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail; mtd->oobavail = chip->ecc.layout->oobavail;
} }
@ -463,7 +463,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *
} }
/* restore ECC layout */ /* restore ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout; chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail; mtd->oobavail = saved_ecc_layout->oobavail;
} }

2
include/configs/ti_armv7_keystone2.h
View File

@ -119,8 +119,6 @@
/* EEPROM definitions */ /* EEPROM definitions */
/* NAND Configuration */ /* NAND Configuration */
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_CS 2