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stm32mp: fdt: update etzpc for STM32MP15x
Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e
This commit is contained in:
Patrick Delaunay
parent
b94b275b0a
commit
ca9c9e7e92
@ -28,13 +28,13 @@
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#define ETZPC_RESERVED 0xffffffff
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#define STM32_FDCAN_BASE 0x4400e000
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#define STM32_CRYP2_BASE 0x4c005000
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#define STM32_CRYP1_BASE 0x54001000
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#define STM32_GPU_BASE 0x59000000
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#define STM32_DSI_BASE 0x5a000000
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#define STM32MP15_FDCAN_BASE 0x4400e000
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#define STM32MP15_CRYP2_BASE 0x4c005000
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#define STM32MP15_CRYP1_BASE 0x54001000
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#define STM32MP15_GPU_BASE 0x59000000
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#define STM32MP15_DSI_BASE 0x5a000000
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static const u32 stm32mp1_ip_addr[] = {
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static const u32 stm32mp15_ip_addr[] = {
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0x5c008000, /* 00 stgenc */
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0x54000000, /* 01 bkpsram */
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0x5c003000, /* 02 iwdg1 */
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@ -44,7 +44,7 @@ static const u32 stm32mp1_ip_addr[] = {
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ETZPC_RESERVED, /* 06 reserved */
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0x54003000, /* 07 rng1 */
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0x54002000, /* 08 hash1 */
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STM32_CRYP1_BASE, /* 09 cryp1 */
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STM32MP15_CRYP1_BASE, /* 09 cryp1 */
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0x5a003000, /* 0A ddrctrl */
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0x5a004000, /* 0B ddrphyc */
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0x5c009000, /* 0C i2c6 */
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@ -97,7 +97,7 @@ static const u32 stm32mp1_ip_addr[] = {
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0x4400b000, /* 3B sai2 */
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0x4400c000, /* 3C sai3 */
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0x4400d000, /* 3D dfsdm */
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STM32_FDCAN_BASE, /* 3E tt_fdcan */
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STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
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ETZPC_RESERVED, /* 3F reserved */
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0x50021000, /* 40 lptim2 */
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0x50022000, /* 41 lptim3 */
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@ -110,7 +110,7 @@ static const u32 stm32mp1_ip_addr[] = {
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0x48003000, /* 48 adc */
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0x4c002000, /* 49 hash2 */
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0x4c003000, /* 4A rng2 */
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STM32_CRYP2_BASE, /* 4B cryp2 */
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STM32MP15_CRYP2_BASE, /* 4B cryp2 */
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ETZPC_RESERVED, /* 4C reserved */
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ETZPC_RESERVED, /* 4D reserved */
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ETZPC_RESERVED, /* 4E reserved */
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@ -163,8 +163,13 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
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int offset, shift;
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u32 addr, status, decprot[ETZPC_DECPROT_NB];
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array = stm32mp1_ip_addr;
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array_size = ARRAY_SIZE(stm32mp1_ip_addr);
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if (IS_ENABLED(CONFIG_STM32MP13x))
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return 0;
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if (IS_ENABLED(CONFIG_STM32MP15x)) {
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array = stm32mp15_ip_addr;
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array_size = ARRAY_SIZE(stm32mp15_ip_addr);
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}
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for (i = 0; i < ETZPC_DECPROT_NB; i++)
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decprot[i] = readl(ETZPC_DECPROT(i));
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@ -248,36 +253,9 @@ static void stm32_fdt_disable_optee(void *blob)
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}
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}
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/*
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* This function is called right before the kernel is booted. "blob" is the
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* device tree that will be passed to the kernel.
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*/
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int ft_system_setup(void *blob, struct bd_info *bd)
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static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
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{
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int ret = 0;
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int soc;
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u32 pkg, cpu;
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char name[SOC_NAME_SIZE];
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if (IS_ENABLED(CONFIG_STM32MP13x))
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return 0;
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soc = fdt_path_offset(blob, "/soc");
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/* when absent, nothing to do */
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if (soc == -FDT_ERR_NOTFOUND)
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return 0;
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if (soc < 0)
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return soc;
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if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
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ret = stm32_fdt_fixup_etzpc(blob, soc);
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if (ret)
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return ret;
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}
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/* MPUs Part Numbers and name*/
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cpu = get_cpu_type();
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get_soc_name(name);
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u32 pkg;
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switch (cpu) {
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case CPU_STM32MP151Fxx:
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@ -287,19 +265,18 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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stm32_fdt_fixup_cpu(blob, name);
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/* after cpu delete we can't trust the soc offsets anymore */
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soc = fdt_path_offset(blob, "/soc");
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stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
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/* fall through */
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stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
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fallthrough;
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case CPU_STM32MP153Fxx:
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case CPU_STM32MP153Dxx:
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case CPU_STM32MP153Cxx:
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case CPU_STM32MP153Axx:
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stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
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stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
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stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
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stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
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break;
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default:
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break;
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}
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switch (cpu) {
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case CPU_STM32MP157Dxx:
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case CPU_STM32MP157Axx:
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@ -307,13 +284,14 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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case CPU_STM32MP153Axx:
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case CPU_STM32MP151Dxx:
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case CPU_STM32MP151Axx:
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stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
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stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
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stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
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name);
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stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
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name);
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break;
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default:
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break;
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}
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switch (get_cpu_package()) {
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case STM32MP15_PKG_AA_LBGA448:
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pkg = STM32MP_PKG_AA;
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@ -337,18 +315,51 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
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"st,package", pkg, false);
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}
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}
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/*
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* TEMP: remove OP-TEE nodes in kernel device tree
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* copied from U-Boot device tree by optee_copy_fdt_nodes
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* when OP-TEE is not detected (probe failed)
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* these OP-TEE nodes are present in <board>-u-boot.dtsi
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* under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
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* when FIP is not used by TF-A
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*/
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if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
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!tee_find_device(NULL, NULL, NULL, NULL))
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stm32_fdt_disable_optee(blob);
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/*
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* This function is called right before the kernel is booted. "blob" is the
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* device tree that will be passed to the kernel.
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*/
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int ft_system_setup(void *blob, struct bd_info *bd)
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{
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int ret = 0;
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int soc;
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u32 cpu;
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char name[SOC_NAME_SIZE];
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soc = fdt_path_offset(blob, "/soc");
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/* when absent, nothing to do */
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if (soc == -FDT_ERR_NOTFOUND)
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return 0;
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if (soc < 0)
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return soc;
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if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
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ret = stm32_fdt_fixup_etzpc(blob, soc);
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if (ret)
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return ret;
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}
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/* MPUs Part Numbers and name*/
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cpu = get_cpu_type();
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get_soc_name(name);
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if (IS_ENABLED(CONFIG_STM32MP15x)) {
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stm32mp15_fdt_fixup(blob, soc, cpu, name);
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/*
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* TEMP: remove OP-TEE nodes in kernel device tree
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* copied from U-Boot device tree by optee_copy_fdt_nodes
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* when OP-TEE is not detected (probe failed)
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* these OP-TEE nodes are present in <board>-u-boot.dtsi
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* under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
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* when FIP is not used by TF-A
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*/
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if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
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!tee_find_device(NULL, NULL, NULL, NULL))
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stm32_fdt_disable_optee(blob);
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}
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return ret;
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}
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