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Merge branch '2022-07-06-platform-updates' into next

Browse Source 
- Assorted updates for Toradex, TI, Aspeed and Nuvoton platforms
This commit is contained in:
Tom Rini 2022-07-06 18:54:29 -04:00
commit cb9843bda3
40 changed files with 921 additions and 216 deletions
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3
.azure-pipelines.yml
View File

@ -261,6 +261,9 @@ stages:
evb_ast2500: evb_ast2500:
TEST_PY_BD: "evb-ast2500" TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu" TEST_PY_ID: "--id qemu"
evb_ast2600:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
vexpress_ca9x4: vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4" TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu" TEST_PY_ID: "--id qemu"

6
.gitlab-ci.yml
View File

@ -272,6 +272,12 @@ evb-ast2500 test.py:
TEST_PY_ID: "--id qemu" TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn <<: *buildman_and_testpy_dfn
evb-ast2600 test.py:
variables:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
sandbox_flattree test.py: sandbox_flattree test.py:
variables: variables:
TEST_PY_BD: "sandbox_flattree" TEST_PY_BD: "sandbox_flattree"

23
arch/arm/dts/ast2500-evb.dts
View File

@ -60,6 +60,10 @@
pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
}; };
&sdmmc {
status = "okay";
};
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
@ -73,3 +77,22 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>; pinctrl-0 = <&pinctrl_sd2_default>;
}; };
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c7 {
status = "okay";
lm75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
};

25
arch/arm/dts/ast2500-u-boot.dtsi
View File

@ -28,31 +28,6 @@
clocks = <&scu ASPEED_CLK_MPLL>; clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst ASPEED_RESET_SDRAM>; resets = <&rst ASPEED_RESET_SDRAM>;
}; };
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst ASPEED_RESET_SDIO>;
};
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst ASPEED_RESET_SDIO>;
};
};
};
}; };
&uart1 { &uart1 {

28
arch/arm/dts/ast2500.dtsi
View File

@ -207,6 +207,34 @@
reg = <0x1e720000 0x9000>; // 36K reg = <0x1e720000 0x9000>; // 36K
}; };
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2500-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
gpio: gpio@1e780000 { gpio: gpio@1e780000 {
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;

49
arch/arm/dts/ast2600-evb.dts
View File

@ -15,9 +15,9 @@
}; };
aliases { aliases {
mmc0 = &emmc_slot0; mmc0 = &emmc;
mmc1 = &sdhci_slot0; mmc1 = &sdhci0;
mmc2 = &sdhci_slot1; mmc2 = &sdhci1;
spi0 = &fmc; spi0 = &fmc;
spi1 = &spi1; spi1 = &spi1;
spi2 = &spi2; spi2 = &spi2;
@ -134,53 +134,52 @@
}; };
}; };
&emmc {
u-boot,dm-pre-reloc; &emmc_controller {
timing-phase = <0x700ff>; status = "okay";
}; };
&emmc_slot0 { &emmc {
u-boot,dm-pre-reloc; non-removable;
status = "okay";
bus-width = <4>; bus-width = <4>;
pinctrl-names = "default"; max-frequency = <100000000>;
pinctrl-0 = <&pinctrl_emmc_default>; clk-phase-mmc-hs200 = <9>, <225>;
sdhci-drive-type = <1>;
}; };
&i2c4 { &i2c4 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
}; };
&i2c5 { &i2c5 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
}; };
&i2c6 { &i2c6 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
}; };
&i2c7 { &i2c7 {
status = "okay"; status = "okay";
pinctrl-names = "default"; temp@2e {
pinctrl-0 = <&pinctrl_i2c8_default>; compatible = "adi,adt7490";
reg = <0x2e>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
}; };
&i2c8 { &i2c8 {
status = "okay"; status = "okay";
pinctrl-names = "default"; lm75@4d {
pinctrl-0 = <&pinctrl_i2c9_default>; compatible = "national,lm75";
reg = <0x4d>;
};
}; };
&mdio0 { &mdio0 {

123
arch/arm/dts/ast2600.dtsi
View File

@ -416,60 +416,51 @@
status = "disabled"; status = "disabled";
}; };
sdhci: sdhci@1e740000 { sdc: sdc@1e740000 {
#interrupt-cells = <1>; compatible = "aspeed,ast2600-sd-controller";
compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; reg = <0x1e740000 0x100>;
reg = <0x1e740000 0x1000>; #address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x100 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
<&scu ASPEED_CLK_GATE_SDEXTCLK>;
clock-names = "ctrlclk", "extclk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e740000 0x1000>;
sdhci_slot0: sdhci_slot0@100 {
compatible = "aspeed,sdhci-ast2600";
reg = <0x100 0x100>;
interrupts = <0>;
interrupt-parent = <&sdhci>;
sdhci,auto-cmd12; sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>; clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled"; status = "disabled";
}; };
sdhci_slot1: sdhci_slot1@200 { sdhci1: sdhci@1e740200 {
compatible = "aspeed,sdhci-ast2600"; compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x200 0x100>; reg = <0x200 0x100>;
interrupts = <1>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sdhci>;
sdhci,auto-cmd12; sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>; clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled"; status = "disabled";
}; };
}; };
emmc: emmc@1e750000 { emmc_controller: sdc@1e750000 {
#interrupt-cells = <1>; compatible = "aspeed,ast2600-sd-controller";
compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; reg = <0x1e750000 0x100>;
reg = <0x1e750000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
<&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
clock-names = "ctrlclk", "extclk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x1e750000 0x1000>; ranges = <0 0x1e750000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>;
emmc_slot0: emmc_slot0@100 {
compatible = "aspeed,emmc-ast2600";
reg = <0x100 0x100>;
interrupts = <0>;
interrupt-parent = <&emmc>;
clocks = <&scu ASPEED_CLK_EMMC>;
status = "disabled"; status = "disabled";
emmc: sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
sdhci,auto-cmd12;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_EMMC>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_default>;
}; };
}; };
@ -832,7 +823,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled"; status = "disabled";
}; };
@ -845,7 +839,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
status = "disabled"; status = "disabled";
}; };
@ -858,7 +855,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
status = "disabled";
}; };
i2c3: i2c@200 { i2c3: i2c@200 {
@ -870,7 +871,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
status = "disabled";
}; };
i2c4: i2c@280 { i2c4: i2c@280 {
@ -882,7 +887,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
status = "disabled";
}; };
i2c5: i2c@300 { i2c5: i2c@300 {
@ -894,7 +903,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
status = "disabled";
}; };
i2c6: i2c@380 { i2c6: i2c@380 {
@ -906,7 +919,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
status = "disabled";
}; };
i2c7: i2c@400 { i2c7: i2c@400 {
@ -918,7 +935,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
status = "disabled";
}; };
i2c8: i2c@480 { i2c8: i2c@480 {
@ -930,7 +951,11 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
status = "disabled";
}; };
i2c9: i2c@500 { i2c9: i2c@500 {
@ -942,7 +967,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled"; status = "disabled";
}; };
@ -955,7 +983,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled"; status = "disabled";
}; };
@ -968,7 +999,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c12_default>;
status = "disabled"; status = "disabled";
}; };
@ -981,7 +1015,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c13_default>;
status = "disabled"; status = "disabled";
}; };
@ -994,7 +1031,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c14_default>;
status = "disabled"; status = "disabled";
}; };
@ -1007,7 +1047,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c15_default>;
status = "disabled"; status = "disabled";
}; };
@ -1020,7 +1063,10 @@
compatible = "aspeed,ast2600-i2c-bus"; compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>; bus-frequency = <100000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>; clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c16_default>;
status = "disabled"; status = "disabled";
}; };
@ -1246,6 +1292,7 @@
function = "I2C1"; function = "I2C1";
groups = "I2C1"; groups = "I2C1";
}; };
pinctrl_i2c2_default: i2c2_default { pinctrl_i2c2_default: i2c2_default {
function = "I2C2"; function = "I2C2";
groups = "I2C2"; groups = "I2C2";

1
arch/arm/dts/k3-am625-r5-sk.dts
View File

@ -28,6 +28,7 @@
/* 2G RAM */ /* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>; reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
u-boot,dm-spl;
}; };
reserved-memory { reserved-memory {

4
arch/arm/dts/k3-am625-sk-u-boot.dtsi
View File

@ -13,6 +13,10 @@
aliases { aliases {
mmc1 = &sdhci1; mmc1 = &sdhci1;
}; };
memory@80000000 {
u-boot,dm-spl;
};
}; };
&cbass_main{ &cbass_main{

2
arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
View File

@ -68,7 +68,7 @@ SECTIONS
_image_binary_end = .; _image_binary_end = .;
.bss __rel_dyn_start (OVERLAY) : { .bss : {
__bss_start = .; __bss_start = .;
*(.bss*) *(.bss*)
. = ALIGN(4); . = ALIGN(4);

2
arch/arm/mach-k3/common.c
View File

@ -516,7 +516,7 @@ void spl_enable_dcache(void)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
dram_init_banksize(); dram_init();
/* reserve TLB table */ /* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_size = PGTABLE_SIZE;

11
arch/arm/mach-k3/j721e_init.c
View File

@ -355,6 +355,17 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
return bootmode; return bootmode;
} }
u32 spl_spi_boot_bus(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT);
return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
}
u32 spl_boot_device(void) u32 spl_boot_device(void)
{ {
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);

4
arch/arm/mach-k3/sysfw-loader.c
View File

@ -324,9 +324,9 @@ static void *k3_sysfw_get_spi_addr(void)
struct udevice *dev; struct udevice *dev;
fdt_addr_t addr; fdt_addr_t addr;
int ret; int ret;
unsigned int sf_bus = spl_spi_boot_bus();
ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, ret = uclass_find_device_by_seq(UCLASS_SPI, sf_bus, &dev);
&dev);
if (ret) if (ret)
return NULL; return NULL;

64
board/ti/am62x/evm.c
View File

@ -9,6 +9,8 @@
#include <asm/io.h> #include <asm/io.h>
#include <spl.h> #include <spl.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
@ -23,17 +25,61 @@ int board_init(void)
int dram_init(void) int dram_init(void)
{ {
gd->ram_size = 0x80000000; return fdtdec_setup_mem_size_base();
return 0;
} }
int dram_init_banksize(void) int dram_init_banksize(void)
{ {
/* Bank 0 declares the memory available in the DDR low region */ return fdtdec_setup_memory_banksize();
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
return 0;
} }
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_K3_AM64_DDRSS)
static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
struct udevice *dev;
int ret;
dram_init_banksize();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
if (ret)
printf("Error fixing up ddr node for ECC use! %d\n", ret);
}
#else
static void fixup_memory_node(struct spl_image_info *spl_image)
{
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int bank;
int ret;
dram_init();
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;
size[bank] = gd->bd->bi_dram[bank].size;
}
/* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
CONFIG_NR_DRAM_BANKS);
if (ret)
printf("Error fixing up memory node! %d\n", ret);
}
#endif
void spl_perform_fixups(struct spl_image_info *spl_image)
{
#if defined(CONFIG_K3_AM64_DDRSS)
fixup_ddr_driver_for_ecc(spl_image);
#else
fixup_memory_node(spl_image);
#endif
}
#endif

39
board/ti/common/board_detect.c
View File

@ -86,7 +86,7 @@ __weak void gpi2c_init(void)
static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
u32 header, u32 size, uint8_t *ep) u32 header, u32 size, uint8_t *ep)
{ {
u32 hdr_read; u32 hdr_read = 0xdeadbeef;
int rc; int rc;
#if CONFIG_IS_ENABLED(DM_I2C) #if CONFIG_IS_ENABLED(DM_I2C)
@ -103,21 +103,25 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
/* /*
* Read the header first then only read the other contents. * Read the header first then only read the other contents.
*/ */
rc = i2c_set_chip_offset_len(dev, 2); rc = i2c_set_chip_offset_len(dev, 1);
if (rc) if (rc)
return rc; return rc;
rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); /*
if (rc) * Skip checking result here since this could be a valid i2c read fail
return rc; * on some boards that use 2 byte addressing.
* We must allow for fall through to check the data if 2 byte
* addressing works
*/
(void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
/* Corrupted data??? */ /* Corrupted data??? */
if (hdr_read != header) { if (hdr_read != header) {
/* /*
* read the eeprom header using i2c again, but use only a * read the eeprom header using i2c again, but use only a
* 1 byte address (some legacy boards need this..) * 2 byte address (some newer boards need this..)
*/ */
rc = i2c_set_chip_offset_len(dev, 1); rc = i2c_set_chip_offset_len(dev, 2);
if (rc) if (rc)
return rc; return rc;
@ -142,19 +146,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
/* /*
* Read the header first then only read the other contents. * Read the header first then only read the other contents.
*/ */
byte = 2; byte = 1;
rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); /*
if (rc) * Skip checking result here since this could be a valid i2c read fail
return rc; * on some boards that use 2 byte addressing.
* We must allow for fall through to check the data if 2 byte
* addressing works
*/
(void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
/* Corrupted data??? */ /* Corrupted data??? */
if (hdr_read != header) { if (hdr_read != header) {
/* /*
* read the eeprom header using i2c again, but use only a * read the eeprom header using i2c again, but use only a
* 1 byte address (some legacy boards need this..) * 2 byte address (some newer boards need this..)
*/ */
byte = 1; byte = 2;
rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
4); 4);
if (rc) if (rc)
@ -434,6 +442,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
struct ti_am6_eeprom_record_board_id board_id; struct ti_am6_eeprom_record_board_id board_id;
struct ti_am6_eeprom_record record; struct ti_am6_eeprom_record record;
int rc; int rc;
int consecutive_bad_records = 0;
/* Initialize with a known bad marker for i2c fails.. */ /* Initialize with a known bad marker for i2c fails.. */
memset(ep, 0, sizeof(*ep)); memset(ep, 0, sizeof(*ep));
@ -470,7 +479,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
*/ */
eeprom_addr = sizeof(board_id); eeprom_addr = sizeof(board_id);
while (true) { while (consecutive_bad_records < 10) {
rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header, rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header,
sizeof(record.header)); sizeof(record.header));
if (rc) if (rc)
@ -506,6 +515,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
pr_err("%s: EEPROM parsing error!\n", __func__); pr_err("%s: EEPROM parsing error!\n", __func__);
return rc; return rc;
} }
consecutive_bad_records = 0;
} else { } else {
/* /*
* We may get here in case of larger records which * We may get here in case of larger records which
@ -513,6 +523,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
*/ */
pr_err("%s: Ignoring record id %u\n", __func__, pr_err("%s: Ignoring record id %u\n", __func__,
record.header.id); record.header.id);
consecutive_bad_records++;
} }
eeprom_addr += record.header.len; eeprom_addr += record.header.len;

32
board/ti/j721e/evm.c
View File

@ -382,19 +382,25 @@ void configure_serdes_torrent(void)
ret = uclass_get_device_by_driver(UCLASS_PHY, ret = uclass_get_device_by_driver(UCLASS_PHY,
DM_DRIVER_GET(torrent_phy_provider), DM_DRIVER_GET(torrent_phy_provider),
&dev); &dev);
if (ret) if (ret) {
printf("Torrent init failed:%d\n", ret); printf("Torrent init failed:%d\n", ret);
return;
}
serdes.dev = dev; serdes.dev = dev;
serdes.id = 0; serdes.id = 0;
ret = generic_phy_init(&serdes); ret = generic_phy_init(&serdes);
if (ret) if (ret) {
printf("phy_init failed!!\n"); printf("phy_init failed!!: %d\n", ret);
return;
}
ret = generic_phy_power_on(&serdes); ret = generic_phy_power_on(&serdes);
if (ret) if (ret) {
printf("phy_power_on failed !!\n"); printf("phy_power_on failed!!: %d\n", ret);
return;
}
} }
void configure_serdes_sierra(void) void configure_serdes_sierra(void)
@ -410,21 +416,27 @@ void configure_serdes_sierra(void)
ret = uclass_get_device_by_driver(UCLASS_MISC, ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(sierra_phy_provider), DM_DRIVER_GET(sierra_phy_provider),
&dev); &dev);
if (ret) if (ret) {
printf("Sierra init failed:%d\n", ret); printf("Sierra init failed:%d\n", ret);
return;
}
count = device_get_child_count(dev); count = device_get_child_count(dev);
for (i = 0; i < count; i++) { for (i = 0; i < count; i++) {
ret = device_get_child(dev, i, &link_dev); ret = device_get_child(dev, i, &link_dev);
if (ret) if (ret) {
printf("probe of sierra child node %d failed\n", i); printf("probe of sierra child node %d failed: %d\n", i, ret);
return;
}
if (link_dev->driver->id == UCLASS_PHY) { if (link_dev->driver->id == UCLASS_PHY) {
link.dev = link_dev; link.dev = link_dev;
link.id = link_count++; link.id = link_count++;
ret = generic_phy_power_on(&link); ret = generic_phy_power_on(&link);
if (ret) if (ret) {
printf("phy_power_on failed !!\n"); printf("phy_power_on failed!!: %d\n", ret);
return;
}
} }
} }
} }

74
board/toradex/common/tdx-cfg-block.c
View File

@ -159,6 +159,42 @@ const char * const toradex_display_adapters[] = {
[159] = "Verdin DSI to LVDS Adapter", [159] = "Verdin DSI to LVDS Adapter",
}; };
const u32 toradex_ouis[] = {
[0] = 0x00142dUL,
[1] = 0x8c06cbUL,
};
static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr)
{
int i;
u32 oui = ntohl(eth_addr->oui) >> 8;
u32 nic = ntohl(eth_addr->nic) >> 8;
for (i = 0; i < ARRAY_SIZE(toradex_ouis); i++) {
if (toradex_ouis[i] == oui)
break;
}
return (u32)((i << 24) + nic);
}
void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr)
{
u8 oui_index = tdx_serial >> 24;
u32 nic = tdx_serial & GENMASK(23, 0);
u32 oui;
if (oui_index >= ARRAY_SIZE(toradex_ouis)) {
puts("Can't find OUI for this serial#\n");
oui_index = 0;
}
oui = toradex_ouis[oui_index];
eth_addr->oui = htonl(oui << 8);
eth_addr->nic = htonl(nic << 8);
}
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
{ {
@ -331,8 +367,7 @@ int read_tdx_cfg_block(void)
memcpy(&tdx_eth_addr, config_block + offset, memcpy(&tdx_eth_addr, config_block + offset,
6); 6);
/* NIC part of MAC address is serial number */ tdx_serial = get_serial_from_mac(&tdx_eth_addr);
tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
break; break;
case TAG_HW: case TAG_HW:
memcpy(&tdx_hw_tag, config_block + offset, 8); memcpy(&tdx_hw_tag, config_block + offset, 8);
@ -354,6 +389,18 @@ out:
return ret; return ret;
} }
static int parse_assembly_string(char *string_to_parse, u16 *assembly)
{
if (string_to_parse[3] >= 'A' && string_to_parse[3] <= 'Z')
*assembly = string_to_parse[3] - 'A';
else if (string_to_parse[3] == '#')
*assembly = dectoul(&string_to_parse[4], NULL);
else
return -EINVAL;
return 0;
}
static int get_cfgblock_interactive(void) static int get_cfgblock_interactive(void)
{ {
char message[CONFIG_SYS_CBSIZE]; char message[CONFIG_SYS_CBSIZE];
@ -362,6 +409,7 @@ static int get_cfgblock_interactive(void)
char wb = 'n'; char wb = 'n';
char mem8g = 'n'; char mem8g = 'n';
int len = 0; int len = 0;
int ret = 0;
/* Unknown module by default */ /* Unknown module by default */
tdx_hw_tag.prodid = 0; tdx_hw_tag.prodid = 0;
@ -545,13 +593,18 @@ static int get_cfgblock_interactive(void)
} }
while (len < 4) { while (len < 4) {
sprintf(message, "Enter the module version (e.g. V1.1B): V"); sprintf(message, "Enter the module version (e.g. V1.1B or V1.1#26): V");
len = cli_readline(message); len = cli_readline(message);
} }
tdx_hw_tag.ver_major = console_buffer[0] - '0'; tdx_hw_tag.ver_major = console_buffer[0] - '0';
tdx_hw_tag.ver_minor = console_buffer[2] - '0'; tdx_hw_tag.ver_minor = console_buffer[2] - '0';
tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
ret = parse_assembly_string(console_buffer, &tdx_hw_tag.ver_assembly);
if (ret) {
printf("Parsing module version failed\n");
return ret;
}
while (len < 8) { while (len < 8) {
sprintf(message, "Enter module serial number: "); sprintf(message, "Enter module serial number: ");
@ -754,6 +807,7 @@ static int get_cfgblock_carrier_interactive(void)
{ {
char message[CONFIG_SYS_CBSIZE]; char message[CONFIG_SYS_CBSIZE];
int len; int len;
int ret = 0;
printf("Supported carrier boards:\n"); printf("Supported carrier boards:\n");
printf("CARRIER BOARD NAME\t\t [ID]\n"); printf("CARRIER BOARD NAME\t\t [ID]\n");
@ -767,13 +821,18 @@ static int get_cfgblock_carrier_interactive(void)
tdx_car_hw_tag.prodid = dectoul(console_buffer, NULL); tdx_car_hw_tag.prodid = dectoul(console_buffer, NULL);
do { do {
sprintf(message, "Enter carrier board version (e.g. V1.1B): V"); sprintf(message, "Enter carrier board version (e.g. V1.1B or V1.1#26): V");
len = cli_readline(message); len = cli_readline(message);
} while (len < 4); } while (len < 4);
tdx_car_hw_tag.ver_major = console_buffer[0] - '0'; tdx_car_hw_tag.ver_major = console_buffer[0] - '0';
tdx_car_hw_tag.ver_minor = console_buffer[2] - '0'; tdx_car_hw_tag.ver_minor = console_buffer[2] - '0';
tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A';
ret = parse_assembly_string(console_buffer, &tdx_car_hw_tag.ver_assembly);
if (ret) {
printf("Parsing module version failed\n");
return ret;
}
while (len < 8) { while (len < 8) {
sprintf(message, "Enter carrier board serial number: "); sprintf(message, "Enter carrier board serial number: ");
@ -950,8 +1009,7 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
} }
/* Convert serial number to MAC address (the storage format) */ /* Convert serial number to MAC address (the storage format) */
tdx_eth_addr.oui = htonl(0x00142dUL << 8); get_mac_from_serial(tdx_serial, &tdx_eth_addr);
tdx_eth_addr.nic = htonl(tdx_serial << 8);
/* Valid Tag */ /* Valid Tag */
write_tag(config_block, &offset, TAG_VALID, NULL, 0); write_tag(config_block, &offset, TAG_VALID, NULL, 0);

2
board/toradex/common/tdx-cfg-block.h
View File

@ -114,4 +114,6 @@ int read_tdx_cfg_block_carrier(void);
int try_migrate_tdx_cfg_block_carrier(void); int try_migrate_tdx_cfg_block_carrier(void);
void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr);
#endif /* _TDX_CFG_BLOCK_H */ #endif /* _TDX_CFG_BLOCK_H */

49
board/toradex/common/tdx-common.c
View File

@ -20,15 +20,17 @@
#include <asm/setup.h> #include <asm/setup.h>
#include "tdx-common.h" #include "tdx-common.h"
#define TORADEX_OUI 0x00142dUL #define SERIAL_STR_LEN 8
#define MODULE_VER_STR_LEN 4 // V1.1
#define MODULE_REV_STR_LEN 3 // [A-Z] or #[26-99]
#ifdef CONFIG_TDX_CFG_BLOCK #ifdef CONFIG_TDX_CFG_BLOCK
static char tdx_serial_str[9]; static char tdx_serial_str[SERIAL_STR_LEN + 1];
static char tdx_board_rev_str[6]; static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
static char tdx_car_serial_str[9]; static char tdx_car_serial_str[SERIAL_STR_LEN + 1];
static char tdx_car_rev_str[6]; static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1];
static char *tdx_carrier_board_name; static char *tdx_carrier_board_name;
#endif #endif
@ -79,21 +81,37 @@ void get_board_serial(struct tag_serialnr *serialnr)
} }
#endif /* CONFIG_SERIAL_TAG */ #endif /* CONFIG_SERIAL_TAG */
static const char *get_board_assembly(u16 ver_assembly)
{
static char ver_name[MODULE_REV_STR_LEN + 1];
if (ver_assembly < 26) {
ver_name[0] = (char)ver_assembly + 'A';
ver_name[1] = '\0';
} else {
snprintf(ver_name, sizeof(ver_name),
"#%u", ver_assembly);
}
return ver_name;
}
int show_board_info(void) int show_board_info(void)
{ {
unsigned char ethaddr[6]; unsigned char ethaddr[6];
if (read_tdx_cfg_block()) { if (read_tdx_cfg_block()) {
printf("MISSING TORADEX CONFIG BLOCK\n"); printf("MISSING TORADEX CONFIG BLOCK\n");
tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); get_mac_from_serial(tdx_serial, &tdx_eth_addr);
tdx_eth_addr.nic = htonl(tdx_serial << 8);
checkboard(); checkboard();
} else { } else {
sprintf(tdx_serial_str, "%08u", tdx_serial); snprintf(tdx_serial_str, sizeof(tdx_serial_str),
sprintf(tdx_board_rev_str, "V%1d.%1d%c", "%08u", tdx_serial);
snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str),
"V%1d.%1d%s",
tdx_hw_tag.ver_major, tdx_hw_tag.ver_major,
tdx_hw_tag.ver_minor, tdx_hw_tag.ver_minor,
(char)tdx_hw_tag.ver_assembly + 'A'); get_board_assembly(tdx_hw_tag.ver_assembly));
env_set("serial#", tdx_serial_str); env_set("serial#", tdx_serial_str);
@ -109,12 +127,13 @@ int show_board_info(void)
tdx_carrier_board_name = (char *) tdx_carrier_board_name = (char *)
toradex_carrier_boards[tdx_car_hw_tag.prodid]; toradex_carrier_boards[tdx_car_hw_tag.prodid];
sprintf(tdx_car_serial_str, "%08u", tdx_car_serial); snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str),
sprintf(tdx_car_rev_str, "V%1d.%1d%c", "%08u", tdx_car_serial);
snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str),
"V%1d.%1d%s",
tdx_car_hw_tag.ver_major, tdx_car_hw_tag.ver_major,
tdx_car_hw_tag.ver_minor, tdx_car_hw_tag.ver_minor,
(char)tdx_car_hw_tag.ver_assembly + get_board_assembly(tdx_car_hw_tag.ver_assembly));
'A');
env_set("carrier_serial#", tdx_car_serial_str); env_set("carrier_serial#", tdx_car_serial_str);
printf("Carrier: Toradex %s %s, Serial# %s\n", printf("Carrier: Toradex %s %s, Serial# %s\n",
@ -170,7 +189,7 @@ int ft_common_board_setup(void *blob, struct bd_info *bd)
if (tdx_hw_tag.ver_major) { if (tdx_hw_tag.ver_major) {
char prod_id[5]; char prod_id[5];
sprintf(prod_id, "%04u", tdx_hw_tag.prodid); snprintf(prod_id, sizeof(prod_id), "%04u", tdx_hw_tag.prodid);
fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5); fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str, fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,

1
common/spl/Kconfig
View File

@ -82,6 +82,7 @@ config SPL_MAX_SIZE
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3 default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
default 0x10000 if ASPEED_AST2600
default 0x0 default 0x0
help help
Maximum size of the SPL image (text, data, rodata, and linker lists Maximum size of the SPL image (text, data, rodata, and linker lists

16
common/spl/spl_spi.c
View File

@ -71,6 +71,16 @@ unsigned int __weak spl_spi_get_uboot_offs(struct spi_flash *flash)
return CONFIG_SYS_SPI_U_BOOT_OFFS; return CONFIG_SYS_SPI_U_BOOT_OFFS;
} }
u32 __weak spl_spi_boot_bus(void)
{
return CONFIG_SF_DEFAULT_BUS;
}
u32 __weak spl_spi_boot_cs(void)
{
return CONFIG_SF_DEFAULT_CS;
}
/* /*
* The main entry for SPI booting. It's necessary that SDRAM is already * The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image * configured and available since this code loads the main U-Boot image
@ -83,15 +93,15 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
unsigned int payload_offs; unsigned int payload_offs;
struct spi_flash *flash; struct spi_flash *flash;
struct image_header *header; struct image_header *header;
unsigned int sf_bus = spl_spi_boot_bus();
unsigned int sf_cs = spl_spi_boot_cs();
/* /*
* Load U-Boot image from SPI flash into RAM * Load U-Boot image from SPI flash into RAM
* In DM mode: defaults speed and mode will be * In DM mode: defaults speed and mode will be
* taken from DT when available * taken from DT when available
*/ */
flash = spi_flash_probe(sf_bus, sf_cs,
flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
CONFIG_SF_DEFAULT_CS,
CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE); CONFIG_SF_DEFAULT_MODE);
if (!flash) { if (!flash) {

1
configs/am62x_evm_r5_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_R5_EVM=y CONFIG_TARGET_AM625_R5_EVM=y
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y

3
configs/evb-ast2500_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set # CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y CONFIG_CMD_MMC=y
@ -35,6 +36,8 @@ CONFIG_CLK=y
CONFIG_ASPEED_GPIO=y CONFIG_ASPEED_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y CONFIG_SYS_I2C_ASPEED=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ASPEED=y CONFIG_MMC_SDHCI_ASPEED=y
CONFIG_PHY_REALTEK=y CONFIG_PHY_REALTEK=y

22
configs/evb-ast2600_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_ASPEED=y CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_TEXT_BASE=0x80000000
@ -20,6 +21,8 @@ CONFIG_SPL_SIZE_LIMIT=0x10000
CONFIG_SPL=y CONFIG_SPL=y
# CONFIG_ARMV7_NONSEC is not set # CONFIG_ARMV7_NONSEC is not set
CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_SYS_LOAD_ADDR=0x83000000
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_FIT_SIGNATURE=y
@ -40,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000
CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_CRC32=y
CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DM_RESET=y CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_SUPPORT=y
@ -47,6 +51,14 @@ CONFIG_SPL_RAM_DEVICE=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y CONFIG_CMD_MMC=y
@ -54,6 +66,11 @@ CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y CONFIG_CMD_MII=y
CONFIG_CMD_PING=y CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_DOS_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@ -64,12 +81,11 @@ CONFIG_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y CONFIG_CLK=y
CONFIG_SPL_CLK=y CONFIG_SPL_CLK=y
CONFIG_DM_HASH=y
CONFIG_HASH_ASPEED=y
CONFIG_ASPEED_ACRY=y
CONFIG_ASPEED_GPIO=y CONFIG_ASPEED_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y
CONFIG_MISC=y CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ASPEED=y CONFIG_MMC_SDHCI_ASPEED=y
CONFIG_PHY_REALTEK=y CONFIG_PHY_REALTEK=y

26
drivers/clk/aspeed/clk_ast2500.c
View File

@ -12,6 +12,7 @@
#include <asm/arch/scu_ast2500.h> #include <asm/arch/scu_ast2500.h>
#include <dm/lists.h> #include <dm/lists.h>
#include <dt-bindings/clock/aspeed-clock.h> #include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/reset/ast2500-reset.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
@ -173,6 +174,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_uart_clk_rate(priv->scu, 5); rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break; break;
default: default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT; return -ENOENT;
} }
@ -425,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
return new_rate; return new_rate;
} }
#define SCU_CLKSTOP_SDIO 27
static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
{
u32 reset_bit;
u32 clkstop_bit;
reset_bit = BIT(ASPEED_RESET_SDIO);
clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
setbits_le32(&scu->sysreset_ctrl1, reset_bit);
udelay(100);
//enable clk
clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
mdelay(10);
clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
return 0;
}
static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
{ {
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@ -438,6 +459,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
new_rate = ast2500_configure_d2pll(priv->scu, rate); new_rate = ast2500_configure_d2pll(priv->scu, rate);
break; break;
default: default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT; return -ENOENT;
} }
@ -479,7 +501,11 @@ static int ast2500_clk_enable(struct clk *clk)
case ASPEED_CLK_D2PLL: case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break; break;
case ASPEED_CLK_GATE_SDCLK:
ast2500_enable_sdclk(priv->scu);
break;
default: default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT; return -ENOENT;
} }

8
drivers/clk/aspeed/clk_ast2600.c
View File

@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk)
rate = ast2600_get_uart_huxclk_rate(priv->scu); rate = ast2600_get_uart_huxclk_rate(priv->scu);
break; break;
default: default:
debug("can't get clk rate\n"); debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT; return -ENOENT;
} }
@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_SDCLK: case ASPEED_CLK_GATE_SDCLK:
ast2600_enable_sdclk(priv->scu); ast2600_enable_sdclk(priv->scu);
break; break;
case ASPEED_CLK_GATE_SDEXTCLK: case ASPEED_CLK_SDIO:
ast2600_enable_extsdclk(priv->scu); ast2600_enable_extsdclk(priv->scu);
break; break;
case ASPEED_CLK_GATE_EMMCCLK: case ASPEED_CLK_GATE_EMMCCLK:
ast2600_enable_emmcclk(priv->scu); ast2600_enable_emmcclk(priv->scu);
break; break;
case ASPEED_CLK_GATE_EMMCEXTCLK: case ASPEED_CLK_EMMC:
ast2600_enable_extemmcclk(priv->scu); ast2600_enable_extemmcclk(priv->scu);
break; break;
case ASPEED_CLK_GATE_FSICLK: case ASPEED_CLK_GATE_FSICLK:
@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk)
ast2600_enable_rsaclk(priv->scu); ast2600_enable_rsaclk(priv->scu);
break; break;
default: default:
pr_err("can't enable clk\n"); debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT; return -ENOENT;
} }

42
drivers/firmware/ti_sci_static_data.h
View File

@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
#if IS_ENABLED(CONFIG_K3_DM_FW) #if IS_ENABLED(CONFIG_K3_DM_FW)
#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) #if IS_ENABLED(CONFIG_SOC_K3_J721E)
static struct ti_sci_resource_static_data rm_static_data[] = { static struct ti_sci_resource_static_data rm_static_data[] = {
/* Free rings */ /* Free rings */
{ {
@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
}, },
{ }, { },
}; };
#endif /* CONFIG_TARGET_J721E_R5_EVM */ #endif /* CONFIG_SOC_K3_J721E */
#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) #if IS_ENABLED(CONFIG_SOC_K3_J721S2)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* Free rings */
{
.dev_id = 235,
.subtype = 1,
.range_start = 124,
.range_num = 32,
},
/* TX channels */
{
.dev_id = 236,
.subtype = 13,
.range_start = 6,
.range_num = 2,
},
/* RX channels */
{
.dev_id = 236,
.subtype = 10,
.range_start = 6,
.range_num = 2,
},
/* RX Free flows */
{
.dev_id = 236,
.subtype = 0,
.range_start = 60,
.range_num = 8,
},
{ },
};
#endif /* CONFIG_TARGET_J7200_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
static struct ti_sci_resource_static_data rm_static_data[] = { static struct ti_sci_resource_static_data rm_static_data[] = {
/* Free rings */ /* Free rings */
{ {
@ -116,7 +82,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
}, },
{ }, { },
}; };
#endif /* CONFIG_TARGET_J721S2_R5_EVM */ #endif /* CONFIG_SOC_K3_J721S2 */
#if IS_ENABLED(CONFIG_SOC_K3_AM625) #if IS_ENABLED(CONFIG_SOC_K3_AM625)
static struct ti_sci_resource_static_data rm_static_data[] = { static struct ti_sci_resource_static_data rm_static_data[] = {

23
drivers/i2c/ast_i2c.c
View File

@ -16,6 +16,7 @@
#include <asm/arch/scu_ast2500.h> #include <asm/arch/scu_ast2500.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
#include <reset.h>
#include "ast_i2c.h" #include "ast_i2c.h"
@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
static int ast_i2c_probe(struct udevice *dev) static int ast_i2c_probe(struct udevice *dev)
{ {
struct ast2500_scu *scu; struct reset_ctl reset_ctl;
int rc;
debug("Enabling I2C%u\n", dev_seq(dev)); debug("Enabling I2C%u\n", dev_seq(dev));
/* /*
* Get all I2C devices out of Reset. * Get all I2C devices out of Reset.
* Only needs to be done once, but doing it for every *
* device does not hurt. * Only needs to be done once so test before performing reset.
*/ */
scu = ast_get_scu(); rc = reset_get_by_index(dev, 0, &reset_ctl);
ast_scu_unlock(scu); if (rc) {
clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C); printf("%s: Failed to get reset signal\n", __func__);
ast_scu_lock(scu); return rc;
}
if (reset_status(&reset_ctl) > 0) {
reset_assert(&reset_ctl);
reset_deassert(&reset_ctl);
}
ast_i2c_init_bus(dev); ast_i2c_init_bus(dev);
@ -343,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = {
static const struct udevice_id ast_i2c_ids[] = { static const struct udevice_id ast_i2c_ids[] = {
{ .compatible = "aspeed,ast2400-i2c-bus" }, { .compatible = "aspeed,ast2400-i2c-bus" },
{ .compatible = "aspeed,ast2500-i2c-bus" }, { .compatible = "aspeed,ast2500-i2c-bus" },
{ .compatible = "aspeed,ast2600-i2c-bus" },
{ }, { },
}; };

6
drivers/misc/Kconfig
View File

@ -326,6 +326,12 @@ config MXC_OCOTP
Programmable memory pages that are stored on the some Programmable memory pages that are stored on the some
Freescale i.MX processors. Freescale i.MX processors.
config NPCM_HOST
bool "Enable support espi or LPC for Host"
depends on REGMAP && SYSCON
help
Enable NPCM BMC espi or LPC support for Host reading and writing.
config SPL_MXC_OCOTP config SPL_MXC_OCOTP
bool "Enable MXC OCOTP driver in SPL" bool "Enable MXC OCOTP driver in SPL"
depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)

1
drivers/misc/Makefile
View File

@ -57,6 +57,7 @@ obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NPCM_OTP) += npcm_otp.o obj-$(CONFIG_NPCM_OTP) += npcm_otp.o
obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o

110
drivers/misc/npcm_host_intf.c Normal file
View File

@ -0,0 +1,110 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Host interface (LPC or eSPI) configuration on Nuvoton BMC
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#include <common.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#define SMC_CTL_REG_ADDR 0xc0001001
#define SMC_CTL_HOSTWAIT 0x80
/* GCR Register Offsets */
#define HIFCR 0x50
#define MFSEL1 0x260
#define MFSEL4 0x26c
/* ESPI Register offsets */
#define ESPICFG 0x4
#define ESPIHINDP 0x80
/* MFSEL bit fileds */
#define MFSEL1_LPCSEL BIT(26)
#define MFSEL4_ESPISEL BIT(8)
/* ESPICFG bit fileds */
#define CHSUPP_MASK GENMASK(27, 24)
#define IOMODE_MASK GENMASK(9, 8)
#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3)
#define MAXFREQ_MASK GENMASK(12, 10)
#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2)
/* ESPIHINDP bit fileds */
#define AUTO_SBLD BIT(4)
#define AUTO_HS1 BIT(8)
#define AUTO_HS2 BIT(12)
#define AUTO_HS3 BIT(16)
static int npcm_host_intf_bind(struct udevice *dev)
{
struct regmap *syscon;
void __iomem *base;
u32 ch_supp, val;
u32 ioaddr;
const char *type;
int ret;
/* Release host wait */
setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
if (IS_ERR(syscon)) {
dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
return PTR_ERR(syscon);
}
ioaddr = dev_read_u32_default(dev, "ioaddr", 0);
if (ioaddr)
regmap_write(syscon, HIFCR, ioaddr);
type = dev_read_string(dev, "type");
if (!type)
return -EINVAL;
if (!strcmp(type, "espi")) {
base = dev_read_addr_ptr(dev);
if (!base)
return -EINVAL;
ret = dev_read_u32(dev, "channel-support", &ch_supp);
if (ret)
return ret;
/* Select eSPI pins function */
regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0);
regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL);
val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp;
writel(val, base + ESPIHINDP);
val = readl(base + ESPICFG);
val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK);
val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp);
writel(val, base + ESPICFG);
} else if (!strcmp(type, "lpc")) {
/* Select LPC pin function */
regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0);
regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
}
return 0;
}
static const struct udevice_id npcm_hostintf_ids[] = {
{ .compatible = "nuvoton,npcm750-host-intf" },
{ .compatible = "nuvoton,npcm845-host-intf" },
{ }
};
U_BOOT_DRIVER(npcm_host_intf) = {
.name = "npcm_host_intf",
.id = UCLASS_MISC,
.of_match = npcm_hostintf_ids,
.bind = npcm_host_intf_bind,
};

1
drivers/mmc/Kconfig
View File

@ -502,6 +502,7 @@ config MMC_SDHCI_ASPEED
depends on ARCH_ASPEED depends on ARCH_ASPEED
depends on DM_MMC depends on DM_MMC
depends on MMC_SDHCI depends on MMC_SDHCI
select MISC
help help
Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
SoCs. This device is compatible with SD 3.0 and/or MMC 4.3 SoCs. This device is compatible with SD 3.0 and/or MMC 4.3

45
drivers/mmc/aspeed_sdhci.c
View File

@ -10,6 +10,7 @@
#include <malloc.h> #include <malloc.h>
#include <sdhci.h> #include <sdhci.h>
#include <linux/err.h> #include <linux/err.h>
#include <dm/lists.h>
struct aspeed_sdhci_plat { struct aspeed_sdhci_plat {
struct mmc_config cfg; struct mmc_config cfg;
@ -26,12 +27,16 @@ static int aspeed_sdhci_probe(struct udevice *dev)
int ret; int ret;
ret = clk_get_by_index(dev, 0, &clk); ret = clk_get_by_index(dev, 0, &clk);
if (ret) if (ret) {
debug("%s: clock get failed %d\n", __func__, ret);
return ret; return ret;
}
ret = clk_enable(&clk); ret = clk_enable(&clk);
if (ret) if (ret) {
debug("%s: clock enable failed %d\n", __func__, ret);
goto free; goto free;
}
host->name = dev->name; host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev); host->ioaddr = dev_read_addr_ptr(dev);
@ -39,6 +44,7 @@ static int aspeed_sdhci_probe(struct udevice *dev)
max_clk = clk_get_rate(&clk); max_clk = clk_get_rate(&clk);
if (IS_ERR_VALUE(max_clk)) { if (IS_ERR_VALUE(max_clk)) {
ret = max_clk; ret = max_clk;
debug("%s: clock rate get failed %d\n", __func__, ret);
goto err; goto err;
} }
@ -89,3 +95,38 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
.priv_auto = sizeof(struct sdhci_host), .priv_auto = sizeof(struct sdhci_host),
.plat_auto = sizeof(struct aspeed_sdhci_plat), .plat_auto = sizeof(struct aspeed_sdhci_plat),
}; };
static int aspeed_sdc_probe(struct udevice *parent)
{
struct clk clk;
int ret;
ret = clk_get_by_index(parent, 0, &clk);
if (ret) {
debug("%s: clock get failed %d\n", __func__, ret);
return ret;
}
ret = clk_enable(&clk);
if (ret) {
debug("%s: clock enable failed %d\n", __func__, ret);
return ret;
}
return 0;
}
static const struct udevice_id aspeed_sdc_ids[] = {
{ .compatible = "aspeed,ast2400-sd-controller" },
{ .compatible = "aspeed,ast2500-sd-controller" },
{ .compatible = "aspeed,ast2600-sd-controller" },
{ }
};
U_BOOT_DRIVER(aspeed_sdc_drv) = {
.name = "aspeed_sdc",
.id = UCLASS_MISC,
.of_match = aspeed_sdc_ids,
.probe = aspeed_sdc_probe,
};

7
drivers/phy/Kconfig
View File

@ -274,6 +274,13 @@ config PHY_MTK_TPHY
multi-ports is first version, otherwise is second veriosn, multi-ports is first version, otherwise is second veriosn,
so you can easily distinguish them by banks layout. so you can easily distinguish them by banks layout.
config PHY_NPCM_USB
bool "Nuvoton NPCM USB PHY support"
depends on PHY
depends on ARCH_NPCM
help
Support the USB PHY in NPCM SoCs
config PHY_IMX8MQ_USB config PHY_IMX8MQ_USB
bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver" bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
depends on PHY depends on PHY

1
drivers/phy/Makefile
View File

@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/ obj-y += cadence/

215
drivers/phy/phy-npcm-usb.c Normal file
View File

@ -0,0 +1,215 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 Nuvoton Technology Corp.
*/
#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
/* GCR Register Offsets */
#define GCR_INTCR3 0x9C
#define GCR_USB1PHYCTL 0x140
#define GCR_USB2PHYCTL 0x144
#define GCR_USB3PHYCTL 0x148
/* USBnPHYCTL bit fields */
#define PHYCTL_RS BIT(28)
#define USBPHY2SW GENMASK(13, 12)
#define USBPHY3SW GENMASK(15, 14)
#define USBPHY2SW_DEV9_PHY1 FIELD_PREP(USBPHY2SW, 0)
#define USBPHY2SW_HOST1 FIELD_PREP(USBPHY2SW, 1)
#define USBPHY2SW_DEV9_PHY2 FIELD_PREP(USBPHY2SW, 3)
#define USBPHY3SW_DEV8_PHY1 FIELD_PREP(USBPHY3SW, 0)
#define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1)
#define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3)
enum controller_id {
UDC0_7,
UDC8,
UDC9,
USBH1,
USBH2,
};
enum phy_id {
PHY1 = 1,
PHY2,
PHY3,
};
/* Phy Switch Settings */
#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */
#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */
#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */
#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */
#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */
#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */
#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */
struct npcm_usbphy {
struct regmap *syscon;
u8 id;
u16 phy_switch; /* (phy_id << 8) | controller_id */
};
static int npcm_usb_phy_init(struct phy *phy)
{
struct npcm_usbphy *priv = dev_get_priv(phy->dev);
struct reset_ctl reset;
int ret;
ret = reset_get_by_index(phy->dev, 0, &reset);
if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret);
return ret;
}
/* setup PHY switch */
switch (priv->phy_switch) {
case USBD8PHY1:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
USBPHY3SW_DEV8_PHY1);
break;
case USBD8PHY3:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
USBPHY3SW_DEV8_PHY3);
break;
case USBD9PHY1:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
USBPHY2SW_DEV9_PHY1);
break;
case USBD9PHY2:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
USBPHY2SW_DEV9_PHY2);
break;
case USBH1PHY2:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
USBPHY2SW_HOST1);
break;
case USBH2PHY3:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
USBPHY3SW_HOST2);
break;
default:
break;
}
/* reset phy */
if (reset_valid(&reset))
reset_assert(&reset);
/* Wait for PHY clocks to stablize for 50us or more */
udelay(100);
/* release phy from reset */
if (reset_valid(&reset))
reset_deassert(&reset);
/* PHY RS bit should be set after reset */
switch (priv->id) {
case PHY1:
regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS);
break;
case PHY2:
regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS);
break;
case PHY3:
regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS);
break;
default:
break;
}
return 0;
}
static int npcm_usb_phy_exit(struct phy *phy)
{
struct npcm_usbphy *priv = dev_get_priv(phy->dev);
/* set PHY switch to default state */
switch (priv->phy_switch) {
case USBD8PHY1:
case USBD8PHY3:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
USBPHY3SW_HOST2);
break;
case USBD9PHY1:
case USBD9PHY2:
regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
USBPHY2SW_HOST1);
break;
default:
break;
}
return 0;
}
static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
{
struct npcm_usbphy *priv = dev_get_priv(phy->dev);
u16 phy_switch;
if (args->args_count < 1 || args->args[0] > USBH2)
return -EINVAL;
phy_switch = (priv->id << 8) | args->args[0];
switch (phy_switch) {
case USBD9PHY1:
case USBH2PHY3:
case USBD8PHY3:
if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX))
return -EINVAL;
case USBDPHY1:
case USBD8PHY1:
case USBD9PHY2:
case USBH1PHY2:
priv->phy_switch = phy_switch;
return 0;
default:
return -EINVAL;
}
}
static int npcm_usb_phy_probe(struct udevice *dev)
{
struct npcm_usbphy *priv = dev_get_priv(dev);
priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon");
if (IS_ERR(priv->syscon)) {
dev_err(dev, "%s: unable to get syscon\n", __func__);
return PTR_ERR(priv->syscon);
}
priv->id = dev_read_u32_default(dev, "reg", -1);
return 0;
}
static const struct udevice_id npcm_phy_ids[] = {
{ .compatible = "nuvoton,npcm845-usb-phy",},
{ .compatible = "nuvoton,npcm750-usb-phy",},
{ }
};
static struct phy_ops npcm_phy_ops = {
.init = npcm_usb_phy_init,
.exit = npcm_usb_phy_exit,
.of_xlate = npcm_usb_phy_xlate,
};
U_BOOT_DRIVER(npcm_phy) = {
.name = "npcm-usb-phy",
.id = UCLASS_PHY,
.of_match = npcm_phy_ids,
.ops = &npcm_phy_ops,
.probe = npcm_usb_phy_probe,
.priv_auto = sizeof(struct npcm_usbphy),
};

19
drivers/reset/reset-ast2500.c
View File

@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
return 0; return 0;
} }
static int ast2500_reset_status(struct reset_ctl *reset_ctl)
{
struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
struct ast2500_scu *scu = priv->scu;
int status;
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
if (reset_ctl->id < 32)
status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1);
else
status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2);
return !!status;
}
static int ast2500_reset_probe(struct udevice *dev) static int ast2500_reset_probe(struct udevice *dev)
{ {
int rc; int rc;
@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = {
struct reset_ops ast2500_reset_ops = { struct reset_ops ast2500_reset_ops = {
.rst_assert = ast2500_reset_assert, .rst_assert = ast2500_reset_assert,
.rst_deassert = ast2500_reset_deassert, .rst_deassert = ast2500_reset_deassert,
.rst_status = ast2500_reset_status,
}; };
U_BOOT_DRIVER(ast2500_reset) = { U_BOOT_DRIVER(ast2500_reset) = {

17
drivers/reset/reset-ast2600.c
View File

@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
return 0; return 0;
} }
static int ast2600_reset_status(struct reset_ctl *reset_ctl)
{
struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
struct ast2600_scu *scu = priv->scu;
int status;
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
if (reset_ctl->id < 32)
status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1);
else
status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2);
return !!status;
}
static int ast2600_reset_probe(struct udevice *dev) static int ast2600_reset_probe(struct udevice *dev)
{ {
int rc; int rc;
@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = {
struct reset_ops ast2600_reset_ops = { struct reset_ops ast2600_reset_ops = {
.rst_assert = ast2600_reset_assert, .rst_assert = ast2600_reset_assert,
.rst_deassert = ast2600_reset_deassert, .rst_deassert = ast2600_reset_deassert,
.rst_status = ast2600_reset_status,
}; };
U_BOOT_DRIVER(ast2600_reset) = { U_BOOT_DRIVER(ast2600_reset) = {

16
drivers/soc/soc_ti_k3.c
View File

@ -64,8 +64,8 @@ static char *j721e_rev_string_map[] = {
"1.0", "1.1", "1.0", "1.1",
}; };
static char *am65x_rev_string_map[] = { static char *typical_rev_string_map[] = {
"1.0", "2.0", "1.0", "2.0", "3.0",
}; };
static const char *get_rev_string(u32 idreg) static const char *get_rev_string(u32 idreg)
@ -82,16 +82,10 @@ static const char *get_rev_string(u32 idreg)
goto bail; goto bail;
return j721e_rev_string_map[rev]; return j721e_rev_string_map[rev];
case AM65X:
if (rev > ARRAY_SIZE(am65x_rev_string_map))
goto bail;
return am65x_rev_string_map[rev];
case AM64X:
case J7200:
default: default:
if (!rev) if (rev > ARRAY_SIZE(typical_rev_string_map))
return "1.0"; goto bail;
return typical_rev_string_map[rev];
}; };
bail: bail:

16
include/spl.h
View File

@ -377,6 +377,22 @@ int spl_load_imx_container(struct spl_image_info *spl_image,
void preloader_console_init(void); void preloader_console_init(void);
u32 spl_boot_device(void); u32 spl_boot_device(void);
/**
* spl_spi_boot_bus() - Lookup function for the SPI boot bus source.
*
* This function returns the SF bus to load from.
* If not overridden, it is weakly defined in common/spl/spl_spi.c.
*/
u32 spl_spi_boot_bus(void);
/**
* spl_spi_boot_cs() - Lookup function for the SPI boot CS source.
*
* This function returns the SF CS to load from.
* If not overridden, it is weakly defined in common/spl/spl_spi.c.
*/
u32 spl_spi_boot_cs(void);
/** /**
* spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source. * spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source.
* @boot_device: ID of the device which the MMC driver wants to read * @boot_device: ID of the device which the MMC driver wants to read