From ce3a98ed92d4b9966d805bf8e7ef569d8ce183eb Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 12 Nov 2022 16:19:45 -0600 Subject: [PATCH] ram: Add BL808 PSRAM driver Signed-off-by: Samuel Holland --- drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 1 + drivers/ram/bflb/Kconfig | 6 + drivers/ram/bflb/Makefile | 8 + drivers/ram/bflb/bl808.h | 171 ++ drivers/ram/bflb/bl808_common.h | 66 + drivers/ram/bflb/bl808_ef_cfg.c | 90 + drivers/ram/bflb/bl808_ef_cfg.h | 67 + drivers/ram/bflb/bl808_ef_ctrl.c | 372 ++++ drivers/ram/bflb/bl808_ef_ctrl.h | 80 + drivers/ram/bflb/bl808_glb.c | 299 +++ drivers/ram/bflb/bl808_glb.h | 2321 +++++++++++++++++++++++ drivers/ram/bflb/bl808_psram_uhs.c | 835 +++++++++ drivers/ram/bflb/bl808_psram_uhs.h | 273 +++ drivers/ram/bflb/bl808_uhs_phy.c | 2780 ++++++++++++++++++++++++++++ drivers/ram/bflb/bl808_uhs_phy.h | 117 ++ drivers/ram/bflb/psram.c | 93 + 17 files changed, 7580 insertions(+) create mode 100644 drivers/ram/bflb/Kconfig create mode 100644 drivers/ram/bflb/Makefile create mode 100644 drivers/ram/bflb/bl808.h create mode 100644 drivers/ram/bflb/bl808_common.h create mode 100644 drivers/ram/bflb/bl808_ef_cfg.c create mode 100644 drivers/ram/bflb/bl808_ef_cfg.h create mode 100644 drivers/ram/bflb/bl808_ef_ctrl.c create mode 100644 drivers/ram/bflb/bl808_ef_ctrl.h create mode 100644 drivers/ram/bflb/bl808_glb.c create mode 100644 drivers/ram/bflb/bl808_glb.h create mode 100644 drivers/ram/bflb/bl808_psram_uhs.c create mode 100644 drivers/ram/bflb/bl808_psram_uhs.h create mode 100644 drivers/ram/bflb/bl808_uhs_phy.c create mode 100644 drivers/ram/bflb/bl808_uhs_phy.h create mode 100644 drivers/ram/bflb/psram.c diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index e085119963b..343bc58b79c 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -108,6 +108,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC. source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/bflb/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 5a39611349d..54e7d000d45 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o +obj-$(CONFIG_RAM_BFLB) += bflb/ obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ diff --git a/drivers/ram/bflb/Kconfig b/drivers/ram/bflb/Kconfig new file mode 100644 index 00000000000..f8e1b9f79d1 --- /dev/null +++ b/drivers/ram/bflb/Kconfig @@ -0,0 +1,6 @@ +config RAM_BFLB + bool "Ram drivers support for Bouffalo Lab SoCs" + depends on RAM && TARGET_BOUFFALO_BL808 + default y + help + This enables support for RAM drivers on Bouffalo Lab SoCs. diff --git a/drivers/ram/bflb/Makefile b/drivers/ram/bflb/Makefile new file mode 100644 index 00000000000..22e93111af3 --- /dev/null +++ b/drivers/ram/bflb/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bl808_ef_cfg.o +obj-y += bl808_ef_ctrl.o +obj-y += bl808_glb.o +obj-y += bl808_psram_uhs.o +obj-y += bl808_uhs_phy.o +obj-y += psram.o diff --git a/drivers/ram/bflb/bl808.h b/drivers/ram/bflb/bl808.h new file mode 100644 index 00000000000..f3ae404e938 --- /dev/null +++ b/drivers/ram/bflb/bl808.h @@ -0,0 +1,171 @@ +#ifndef __BL808_H__ +#define __BL808_H__ + +#include +#include + +#define ARCH_RISCV +#define CPU_M0 + +#define __ASM asm +#define __NOP barrier + +#define arch_delay_us(x) udelay(x) + +#define readl(a) readl((const volatile void __iomem *)a) +#define writel(v, a) writel(v, (volatile void __iomem *)a) + +/** + * @brief BL808 Memory Map Definitions + */ +#define BL808_OCRAM_BASE (0x22020000) +#define BL808_OCRAM_END (0x22020000 + 64 * 1024) +#define BL808_OCRAM_CACHEABLE_BASE (0x62020000) +#define BL808_OCRAM_CACHEABLE_END (0x62020000 + 64 * 1024) + +#define BL808_WRAM_BASE (0x22030000) +#define BL808_WRAM_END (0x22030000 + 160 * 1024) +#define BL808_WRAM_CACHEABLE_BASE (0x62030000) +#define BL808_WRAM_CACHEABLE_END (0x62030000 + 160 * 1024) + +#define BL808_MCU_ALLRAM_BASE (0x22020000) +#define BL808_MCU_ALLRAM_END (0x22020000 + 64 * 1024 + 160 * 1024) +#define BL808_MCU_ALLRAM_CACHEABLE_BASE (0x62020000) +#define BL808_MCU_ALLRAM_CACHEABLE_END (0x62020000 + 64 * 1024 + 160 * 1024) + +#define BL808_DRAM_BASE (0x3EF80000) +#define BL808_DRAM_END (0x3EF80000 + 512 * 1024) +#define BL808_DRAM_CACHEABLE_BASE (0x7EF80000) +#define BL808_DRAM_CACHEABLE_END (0x7EF80000 + 512 * 1024) + +#define BL808_VRAM_BASE (0x3F000000) +#define BL808_VRAM_END (0x3F000000 + 32 * 1024) +#define BL808_VRAM_CACHEABLE_BASE (0x7F000000) +#define BL808_VRAM_CACHEABLE_END (0x7F000000 + 32 * 1024) + +#define BL808_MM_ALLRAM_BASE (0x3EF80000) +#define BL808_MM_ALLRAM_END (0x3EF80000 + 512 * 1024 + 32 * 1024) +#define BL808_MM_ALLRAM_CACHEABLE_BASE (0x7EF80000) +#define BL808_MM_ALLRAM_CACHEABLE_END (0x7EF80000 + 512 * 1024 + 32 * 1024) + +#define BL808_FLASH_XIP_BASE (0x58000000) +#define BL808_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024) +#define BL808_FLASH2_XIP_BASE (0x5C000000) +#define BL808_FLASH2_XIP_END (0x5C000000 + 64 * 1024 * 1024) +#define BL808_FLASH_XIP_REMAP0_BASE (0xD8000000) +#define BL808_FLASH_XIP_REMAP0_END (0xD8000000 + 64 * 1024 * 1024) +#define BL808_FLASH2_XIP_REMAP0_BASE (0xDC000000) +#define BL808_FLASH2_XIP_REMAP0_END (0xDC000000 + 64 * 1024 * 1024) + +#define BL808_MM_WHOLERAM_BASE (0x3EF80000) +#define BL808_MM_WHOLERAM_END (0x3EF80000 + 512 * 1024 + 96 * 1024) +#define BL808_MM_WHOLERAM_CACHEABLE_BASE (0x7EF80000) +#define BL808_MM_WHOLERAM_CACHEABLE_END (0x7EF80000 + 512 * 1024 + 96 * 1024) + +/*@} end of group Memory_Map_Section */ + +/* BL808 peripherals base address */ +/* WLSYS */ +#define GLB_BASE ((uint32_t)0x20000000) +#define MIX_BASE ((uint32_t)0x20001000) +#define GPIP_BASE ((uint32_t)0x20002000) +#define PHY_BASE ((uint32_t)0x20002800) +#define AGC_BASE ((uint32_t)0x20002c00) +#define SEC_DBG_BASE ((uint32_t)0x20003000) +#define SEC_ENG_BASE ((uint32_t)0x20004000) +#define TZ1_BASE ((uint32_t)0x20005000) +#define TZC_SEC_BASE ((uint32_t)0x20005000) +#define TZ2_BASE ((uint32_t)0x20006000) +#define TZC_NSEC_BASE ((uint32_t)0x20006000) +#define EFUSE_BASE ((uint32_t)0x20056000) +#define EF_DATA_BASE ((uint32_t)0x20056000) +#define EF_CTRL_BASE ((uint32_t)0x20056000) +#define CCI_BASE ((uint32_t)0x20008000) +#define MCU_MISC_BASE ((uint32_t)0x20009000) +#define L1C_BASE ((uint32_t)0x20009000) +#define UART0_BASE ((uint32_t)0x2000a000) +#define UART1_BASE ((uint32_t)0x2000a100) +#define SPI0_BASE ((uint32_t)0x2000a200) +#define I2C0_BASE ((uint32_t)0x2000a300) +#define PWM_BASE ((uint32_t)0x2000a400) +#define TIMER0_BASE ((uint32_t)0x2000a500) +#define IR_BASE ((uint32_t)0x2000a600) +#define CKS_BASE ((uint32_t)0x2000a700) +#define IPC0_BASE ((uint32_t)0x2000a800) +#define IPC1_BASE ((uint32_t)0x2000a840) +#define I2C1_BASE ((uint32_t)0x2000a900) +#define UART2_BASE ((uint32_t)0x2000aa00) +#define ISO11898_BASE ((uint32_t)0x2000aa00) +#define I2S_BASE ((uint32_t)0x2000ab00) +#define PDM0_BASE ((uint32_t)0x2000a000) +#define LZ4D_BASE ((uint32_t)0x2000ad00) +#define QSPI_BASE ((uint32_t)0x2000b000) +#define SF_CTRL_BASE ((uint32_t)0x2000b000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600) +#define DMA0_BASE ((uint32_t)0x2000c000) +#define PDS_BASE ((uint32_t)0x2000e000) +#define HBN_BASE ((uint32_t)0x2000f000) +#define AON_BASE ((uint32_t)0x2000f000) +#define EMI_MISC_BASE ((uint32_t)0x20050000) +#define PSRAM_CTRL_BASE ((uint32_t)0x20052000) +#define USB_BASE ((uint32_t)0x20072000) +#define AUDIO_BASE ((uint32_t)0x20055000) +#define SDH_BASE ((uint32_t)0x20060000) +#define EMAC_BASE ((uint32_t)0x20070000) +#define DMA1_BASE ((uint32_t)0x20071000) + +/* MMSYS */ +#define MM_MISC_BASE ((uint32_t)0x30000000) +#define DMA2_BASE ((uint32_t)0x30001000) +#define UART3_BASE ((uint32_t)0x30002000) +#define I2C2_BASE ((uint32_t)0x30003000) +#define I2C3_BASE ((uint32_t)0x30004000) +#define IPC2_BASE ((uint32_t)0x30005000) +#define DMA2D_BASE ((uint32_t)0x30006000) +#define CLKRST_CTRL_BASE ((uint32_t)0x30007000) +#define MM_GLB_BASE ((uint32_t)0x30007000) +#define SPI1_BASE ((uint32_t)0x30008000) +#define TIMER1_BASE ((uint32_t)0x30009000) +#define PSRAM_UHS_BASE ((uint32_t)0x3000f000) + +/* SUBSYS */ +#define SUB_MISC_BASE ((uint32_t)0x30010000) +#define SUB_BASE ((uint32_t)0x30011000) +#define DVP0_BASE ((uint32_t)0x30012000) +#define DVP1_BASE ((uint32_t)0x30012100) +#define DVP2_BASE ((uint32_t)0x30012200) +#define DVP3_BASE ((uint32_t)0x30012300) +#define DVP4_BASE ((uint32_t)0x30012400) +#define DVP5_BASE ((uint32_t)0x30012500) +#define DVP6_BASE ((uint32_t)0x30012600) +#define DVP7_BASE ((uint32_t)0x30012700) +#define DVP_TSRC0_BASE ((uint32_t)0x30012800) +#define DVP_TSRC1_BASE ((uint32_t)0x30012900) +#define AXI_CTRL_NR3D_BASE ((uint32_t)0x30012a00) +#define OSD_PROBE_BASE ((uint32_t)0x30012b00) +#define OSD_A_BASE ((uint32_t)0x30013000) +#define OSD_B_BASE ((uint32_t)0x30014000) +#define OSD_DP_BASE ((uint32_t)0x30015000) +#define OSD_BLEND0_OFFSET (0x000) +#define OSD_BLEND1_OFFSET (0x100) +#define OSD_BLEND2_OFFSET (0x200) +#define OSD_BLEND3_OFFSET (0x300) +#define OSD_DRAW_LOW_OFFSET (0x400) +#define OSD_DRAW_HIGH_OFFSET (0x504) +#define MIPI_BASE ((uint32_t)0x3001a000) +#define DBI_BASE ((uint32_t)0x3001b000) +#define DSI_BASE ((uint32_t)0x3001a100) +#define CSI_BASE ((uint32_t)0x3001a000) + +/* CODEC_SUBSYS */ +#define CODEC_MISC_BASE ((uint32_t)0x30020000) +#define MJPEG_BASE ((uint32_t)0x30021000) +#define VIDEO_BASE ((uint32_t)0x30022000) +#define MJPEG_DEC_BASE ((uint32_t)0x30023000) +#define BL_CNN_BASE ((uint32_t)0x30024000) + +#define HBN_RAM_BASE ((uint32_t)0x20010000) + +#define RF_BASE ((uint32_t)0x20001000) + +#endif diff --git a/drivers/ram/bflb/bl808_common.h b/drivers/ram/bflb/bl808_common.h new file mode 100644 index 00000000000..fefd5904e83 --- /dev/null +++ b/drivers/ram/bflb/bl808_common.h @@ -0,0 +1,66 @@ +#ifndef __BL808_COMMON_H__ +#define __BL808_COMMON_H__ + +#include "bl808.h" + +/** + * @brief Memory access macro + */ +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) + +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) +#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) +#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) +#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) +#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) +#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) + +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; + +/** + * @brief Functional type definition + */ +typedef enum { + DISABLE = 0, + ENABLE = 1, +} BL_Fun_Type; + +/** + * @brief Status type definition + */ +typedef enum { + RESET = 0, + SET = 1, +} BL_Sts_Type; + +/** + * @brief Mask type definition + */ +typedef enum { + UNMASK = 0, + MASK = 1 +} BL_Mask_Type; + +#define CHECK_PARAM(expr) ((void)0) + +#endif /* __BL808_COMMON_H__ */ diff --git a/drivers/ram/bflb/bl808_ef_cfg.c b/drivers/ram/bflb/bl808_ef_cfg.c new file mode 100644 index 00000000000..a698ff12efc --- /dev/null +++ b/drivers/ram/bflb/bl808_ef_cfg.c @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file bl808_ef_cfg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl808_ef_ctrl.h" +#include "bl808_ef_cfg.h" +#include +#include + +#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() +#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() + +/****************************************************************************/ /** + * @brief Efuse get chip info + * + * @param chipInfo: info pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); + chipInfo->chipInfo = (tmpVal>>29)&0x7; + chipInfo->memoryInfo = (tmpVal>>27)&0x3; + chipInfo->psramInfo = (tmpVal>>25)&0x3; + chipInfo->deviceInfo = (tmpVal>>22)&0x7; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); + chipInfo->psramInfo |= ((tmpVal>>20)&0x1) << 2; +} + +/****************************************************************************/ /** + * @brief Efuse read psram trim configuration + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R1; + + tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2); + trim->psramTrim = (tmpVal >> 0) & 0x7ff; + trim->psramTrimParity = (tmpVal >> 11) & 0x01; + trim->psramTrimEn = (tmpVal >> 12) & 0x01; +} diff --git a/drivers/ram/bflb/bl808_ef_cfg.h b/drivers/ram/bflb/bl808_ef_cfg.h new file mode 100644 index 00000000000..2c2debd9bea --- /dev/null +++ b/drivers/ram/bflb/bl808_ef_cfg.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file bl808_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL808_EF_CFG_H__ +#define __BL808_EF_CFG_H__ + +#include +#include "bl808_common.h" + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint8_t chipInfo; /*!< Efuse chip revision */ + uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */ + uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:WB 4MB, 2:UHS 32MB, 3:UHS 64MB, 4:WB 32MB */ + uint8_t deviceInfo; /*!< Efuse device information */ +} Efuse_Chip_Info_Type; + +/** + * @brief Efuse psram trim type definition + */ +typedef struct +{ + uint32_t psramTrim : 11; /*!< Efuse analog trim:psram trim date */ + uint32_t psramTrimParity : 1; /*!< Efuse analog trim:psram trim_parity */ + uint32_t psramTrimEn : 1; /*!< Efuse analog trim:psram trim_en */ + uint32_t reserved : 19; /*!< Efuse analog trim:reserved */ +} Efuse_Psram_Trim_Type; + +void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo); +void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim); + +#endif /* __BL808_EF_CFG_H__ */ diff --git a/drivers/ram/bflb/bl808_ef_ctrl.c b/drivers/ram/bflb/bl808_ef_ctrl.c new file mode 100644 index 00000000000..f1a030d1d60 --- /dev/null +++ b/drivers/ram/bflb/bl808_ef_ctrl.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file bl808_ef_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl808_ef_ctrl.h" +#include +#include + +/** @addtogroup BL808_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_EF_CTRL + * @{ + */ + +/** @defgroup SEC_EF_CTRL_Private_Macros + * @{ + */ +#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) +#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) +#define EF_CTRL_DFT_TIMEOUT_VAL (320 * 1000) +#ifndef BOOTROM +#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() +#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() +#else +#define EF_CTRL_LOAD_BEFORE_READ_R0 +#define EF_CTRL_LOAD_BEFORE_READ_R1 +#endif +#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, 0, EF_CTRL_EFUSE_R0_SIZE / 4) +#define EF_CTRL_DATA1_CLEAR EF_Ctrl_Clear(1, 0, EF_CTRL_EFUSE_R1_SIZE / 4) + +/*@} end of group SEC_EF_CTRL_Private_Macros */ + +/** @defgroup SEC_EF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Types */ + +/** @defgroup SEC_EF_CTRL_Private_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Variables */ + +/** @defgroup SEC_EF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Global_Variables */ + +/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SEC_EF_CTRL_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Switch efuse region 0 control to AHB clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +void EF_Ctrl_Sw_AHB_Clk_0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + while (EF_Ctrl_Busy() == SET) { + timeout--; + + if (timeout == 0) { + break; + } + } + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Switch efuse region 1 control to AHB clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +void EF_Ctrl_Sw_AHB_Clk_1(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + while (EF_Ctrl_Busy() == SET) { + timeout--; + + if (timeout == 0) { + break; + } + } + + /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, + so we select it(them) in ef_if_ctrl_0 */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_1_RW_POS) | + (0 << EF_CTRL_EF_IF_1_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Load efuse region 0 + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +void EF_Ctrl_Load_Efuse_R0(void) +{ + uint32_t tmpVal; + uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; + + EF_CTRL_DATA0_CLEAR; + + /* Trigger read */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (1 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + arch_delay_us(10); + + /* Wait for efuse control idle */ + do { + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + timeout--; + + if (timeout == 0) { + break; + } + } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || + + (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); + + /* Switch to AHB clock */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Load efuse region 1 + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +void EF_Ctrl_Load_Efuse_R1(void) +{ + uint32_t tmpVal; + + EF_CTRL_DATA1_CLEAR; + + /* Trigger read */ + /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, + so we select it(them) in ef_if_ctrl_0 */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_1_RW_POS) | + (0 << EF_CTRL_EF_IF_1_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_1_RW_POS) | + (1 << EF_CTRL_EF_IF_1_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); + + arch_delay_us(10); + + /* Wait for efuse control idle */ + do { + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1); + } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_1_BUSY)); + + do { + tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); + } while (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)); + + /* Switch to AHB clock since often read efuse data after load */ + /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, + so we select it(them) in ef_if_ctrl_0 */ + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | + (0 << EF_CTRL_EF_IF_POR_DIG_POS) | + (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_0_RW_POS) | + (0 << EF_CTRL_EF_IF_0_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); + + tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | + (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | + (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | + (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | + (0 << EF_CTRL_EF_IF_1_RW_POS) | + (0 << EF_CTRL_EF_IF_1_TRIG_POS); + BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Check efuse busy status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +BL_Sts_Type EF_Ctrl_Busy(void) +{ + if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY) || + BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1), EF_CTRL_EF_IF_1_BUSY)) { + return SET; + } + + return RESET; +} +#endif + +/****************************************************************************/ /** + * @brief Clear efuse data register + * + * @param region: index efuse region + * @param index: index of efuse in word + * @param len: data length + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len) +{ + uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); + uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); + uint32_t i = 0; + + if (region == 0) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Clear data */ + for (i = 0; i < len; i++) { + pEfuseStart0[index + i] = 0; + } + } else if (region == 1) { + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_1(); + + /* Clear data */ + for (i = 0; i < len; i++) { + pEfuseStart1[index + i] = 0; + } + } +} +#endif diff --git a/drivers/ram/bflb/bl808_ef_ctrl.h b/drivers/ram/bflb/bl808_ef_ctrl.h new file mode 100644 index 00000000000..82e6ee946e5 --- /dev/null +++ b/drivers/ram/bflb/bl808_ef_ctrl.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file bl808_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL808_EF_CTRL_H__ +#define __BL808_EF_CTRL_H__ + +#include +#include "bl808_common.h" + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +} EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +} EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd : 22; /*!< Reserved */ + uint32_t deviceInfo : 3; /*!< Efuse device information */ + uint32_t psramInfo : 2; /*!< Efuse psram info 0:no psram, 1:BW 4MB, 2:UHS 64MB */ + uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 8:1MB flash */ + uint32_t chipInfo : 3; /*!< Efuse chip revision */ +} Efuse_Device_Info_Type; + +#define EF_CTRL_EFUSE_R0_SIZE 128 +#define EF_CTRL_EFUSE_R1_SIZE 128 + +void EF_Ctrl_Load_Efuse_R0(void); +void EF_Ctrl_Load_Efuse_R1(void); +BL_Sts_Type EF_Ctrl_Busy(void); +void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len); +void EF_Ctrl_Sw_AHB_Clk_0(void); +void EF_Ctrl_Sw_AHB_Clk_1(void); + +#endif /* __BL808_EF_CTRL_H__ */ diff --git a/drivers/ram/bflb/bl808_glb.c b/drivers/ram/bflb/bl808_glb.c new file mode 100644 index 00000000000..76ad7a7a082 --- /dev/null +++ b/drivers/ram/bflb/bl808_glb.c @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file bl808_glb_pll.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include +#include "bl808_glb.h" + +/* uhs PLL 2000 Config*/ +const GLB_MU_PLL_CFG_BASIC_Type uhsPll2000BasicCfg_24M = { + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_CFG_BASIC_Type uhsPll2000BasicCfg_32M = { + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_CFG_BASIC_Type uhsPll2000BasicCfg_38P4M = { + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_CFG_BASIC_Type uhsPll2000BasicCfg_40M = { + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_CFG_BASIC_Type uhsPll2000BasicCfg_26M = { + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ +}; +const GLB_MU_PLL_Cfg_Type uhsPllCfg_2000M[GLB_XTAL_MAX] = { + { NULL, 0x0 }, /*!< XTAL is None */ + { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ + { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ + { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ + { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ + { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ + { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ +}; + +/****************************************************************************/ /** + * @brief GLB power off mipi uhs PLL + * + * @param pllType: PLL XTAL type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType) +{ + uint32_t REG_PLL_BASE_ADDRESS = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType)); + + switch (pllType) { + case GLB_MU_PLL_MIPIPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + case GLB_MU_PLL_UHSPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; + break; + default: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + } + + /* cfg0 : pu_aupll=0 */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + /* cfg0 : pu_aupll_sfreg=0 */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB mipi uhs PLL ref clock select + * + * @param pllType: PLL XTAL type + * @param refClk: PLL ref clock select + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) +{ + uint32_t REG_PLL_BASE_ADDRESS = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); + CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); + + switch (pllType) { + case GLB_MU_PLL_MIPIPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + case GLB_MU_PLL_UHSPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; + break; + default: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + } + + /* xxxpll_refclk_sel */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB power on PLL + * + * @param pllType: PLL XTAL type + * @param cfg: GLB PLL configuration + * @param waitStable: wait PLL stable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable) +{ + uint32_t REG_PLL_BASE_ADDRESS = 0; + uint32_t tmpVal = 0; + + /* unknown */ + CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); + + switch (pllType) { + case GLB_MU_PLL_MIPIPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + case GLB_MU_PLL_UHSPLL: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; + break; + default: + REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; + break; + } + + /* Step1:config parameter */ + /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); + + /* cfg4:Set aupll_sel_sample_clk */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); + + /* cfg5:Set aupll_vco_speed */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); + + /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */ + if (GLB_MU_PLL_UHSPLL == pllType) { + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); + } + + /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); + + /* Step2:config pu */ + /* cfg0 : pu_aupll_sfreg=1 */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + /* delay > 2us */ + arch_delay_us(3); + + /* cfg0 : pu_wifipll=1 */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + /* delay > 2us */ + arch_delay_us(3); + + /* toggle sdm_reset (pulse 0 > 1us) */ + /* cfg0 : aupll_sdm_reset */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + arch_delay_us(2); + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + arch_delay_us(2); + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + /* Step3:reset pll */ + /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + arch_delay_us(2); + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + arch_delay_us(2); + tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); + BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); + + if (waitStable) { + /* Wait 1.5*30us */ + arch_delay_us(45); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief reconfigure UHSPLL clock + * + * @param xtalType: XTAL frequency type + * @param pllCfg: PLL configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) +{ + GLB_PLL_REF_CLK_Type refClk; + + if (xtalType == GLB_XTAL_RC32M) { + refClk = GLB_PLL_REFCLK_RC32M; + } else { + refClk = GLB_PLL_REFCLK_XTAL; + } + + GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); + GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); + GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1); + + return SUCCESS; +} diff --git a/drivers/ram/bflb/bl808_glb.h b/drivers/ram/bflb/bl808_glb.h new file mode 100644 index 00000000000..ab255d1ffcd --- /dev/null +++ b/drivers/ram/bflb/bl808_glb.h @@ -0,0 +1,2321 @@ +/** + ****************************************************************************** + * @file bl808_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL808_GLB_H__ +#define __BL808_GLB_H__ + +#include +#include "bl808_common.h" + +/** @addtogroup BL808_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB AHB clock IP type definition + */ +typedef enum { + GLB_AHB_CLOCK_IP_CPU, + GLB_AHB_CLOCK_IP_SDU, + GLB_AHB_CLOCK_IP_SEC, + GLB_AHB_CLOCK_IP_DMA_0, + GLB_AHB_CLOCK_IP_DMA_1, + GLB_AHB_CLOCK_IP_DMA_2, + GLB_AHB_CLOCK_IP_CCI, + GLB_AHB_CLOCK_IP_RF_TOP, + GLB_AHB_CLOCK_IP_GPIP, + GLB_AHB_CLOCK_IP_TZC, + GLB_AHB_CLOCK_IP_EF_CTRL, + GLB_AHB_CLOCK_IP_SF_CTRL, + GLB_AHB_CLOCK_IP_EMAC, + GLB_AHB_CLOCK_IP_UART0, + GLB_AHB_CLOCK_IP_UART1, + GLB_AHB_CLOCK_IP_UART2, + GLB_AHB_CLOCK_IP_UART3, + GLB_AHB_CLOCK_IP_SPI, + GLB_AHB_CLOCK_IP_I2C, + GLB_AHB_CLOCK_IP_PWM, + GLB_AHB_CLOCK_IP_TIMER, + GLB_AHB_CLOCK_IP_IR, + GLB_AHB_CLOCK_IP_CHECKSUM, + GLB_AHB_CLOCK_IP_QDEC, + GLB_AHB_CLOCK_IP_KYS, + GLB_AHB_CLOCK_IP_I2S, + GLB_AHB_CLOCK_IP_USB11, + GLB_AHB_CLOCK_IP_CAM, + GLB_AHB_CLOCK_IP_MJPEG, + GLB_AHB_CLOCK_IP_BT_BLE_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_LP, + GLB_AHB_CLOCK_IP_ZB_NORMAL, + GLB_AHB_CLOCK_IP_ZB_LP, + GLB_AHB_CLOCK_IP_WIFI_NORMAL, + GLB_AHB_CLOCK_IP_WIFI_LP, + GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_2_LP, + GLB_AHB_CLOCK_IP_EMI_MISC, + GLB_AHB_CLOCK_IP_PSRAM0_CTRL, + GLB_AHB_CLOCK_IP_PSRAM1_CTRL, + GLB_AHB_CLOCK_IP_USB20, + GLB_AHB_CLOCK_IP_MIX2, + GLB_AHB_CLOCK_IP_AUDIO, + GLB_AHB_CLOCK_IP_SDH, + GLB_AHB_CLOCK_IP_ZB2_NORMAL, + GLB_AHB_CLOCK_IP_ZB2_LP, + GLB_AHB_CLOCK_IP_I2C1, + GLB_AHB_CLOCK_IP_WIFI_PHY, + GLB_AHB_CLOCK_IP_WIFI_MAC_PHY, + GLB_AHB_CLOCK_IP_WIFI_PLATFORM, + GLB_AHB_CLOCK_IP_LZ4, + GLB_AHB_CLOCK_IP_AUPDM, + GLB_AHB_CLOCK_IP_GAUGE, +} GLB_AHB_CLOCK_IP_Type; + +/** + * @brief GLB core ID type definition + */ +typedef enum { + GLB_CORE_ID_M0, /*!< M0 */ + GLB_CORE_ID_D0, /*!< D0 */ + GLB_CORE_ID_LP, /*!< LP */ + GLB_CORE_ID_MAX, /*!< ID max */ + GLB_CORE_ID_INVALID, /*!< ID invalid */ +} GLB_CORE_ID_Type; + +/** + * @brief cci ID type definition + */ +typedef enum { + CCI0_ID, /*!< CCI0 port define */ + CCI_ID_MAX, /*!< CCI MAX ID define */ +} CCI_ID_Type; + +/** + * @brief GLB DSP all interrupt type definition + */ +typedef enum { + GLB_DSP_ALL_INT_BUS_DEC_ERR_INT = 0, /*!< bus_dec_err_int */ + GLB_DSP_ALL_INT_RSV1_INT = 1, /*!< rsv1 */ + GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ = 2, /*!< |ipc2_np2ap_irq */ + GLB_DSP_ALL_INT_RSV3 = 3, /*!< rsv3 */ + GLB_DSP_ALL_INT_UART0_INT = 4, /*!< uart0_int */ + GLB_DSP_ALL_INT_I2C0_INT = 5, /*!< i2c0_int */ + GLB_DSP_ALL_INT_I2C1_INT = 6, /*!< i2c1_int */ + GLB_DSP_ALL_INT_SPI_INT = 7, /*!< spi_int */ + GLB_DSP_ALL_INT_RSV4_INT = 8, /*!< rsv4 */ + GLB_DSP_ALL_INT_RSV5_INT = 9, /*!< rsv5 */ + GLB_DSP_ALL_INT_SEOF1_INT = 10, /*!< seof1_int */ + GLB_DSP_ALL_INT_SEOF2_INT = 11, /*!< seof2_int */ + GLB_DSP_ALL_INT_SEOF3_INT = 12, /*!< seof3_int */ + GLB_DSP_ALL_INT_DVP2BUS_INT_0 = 13, /*!< dvp2bus_int[0] */ + GLB_DSP_ALL_INT_DVP2BUS_INT_1 = 14, /*!< dvp2bus_int[1] */ + GLB_DSP_ALL_INT_DVP2BUS_INT_2 = 15, /*!< dvp2bus_int[2] */ + GLB_DSP_ALL_INT_DVP2BUS_INT_3 = 16, /*!< dvp2bus_int[3] */ + GLB_DSP_ALL_INT_H264_BS_IRQ = 17, /*!< h264_bs_irq */ + GLB_DSP_ALL_INT_H264_FRAME_IRQ = 18, /*!< h264_frame_irq */ + GLB_DSP_ALL_INT_H264_SEQ_DONE_INT = 19, /*!< h264_seq_done_int */ + GLB_DSP_ALL_INT_MJPEG_INT = 20, /*!< mjpeg_int */ + GLB_DSP_ALL_INT_H264_S_BS_IRQ = 21, /*!< h264_s_bs_irq */ + GLB_DSP_ALL_INT_H264_S_FRAME_IRQ = 22, /*!< h264_s_frame_irq */ + GLB_DSP_ALL_INT_H264_S_SEQ_DONE_INT = 23, /*!< h264_s_seq_done_int */ + GLB_DSP_ALL_INT_DMA_INTR_0 = 24, /*!< DMA_INTR[0] */ + GLB_DSP_ALL_INT_DMA_INTR_1 = 25, /*!< DMA_INTR[1] */ + GLB_DSP_ALL_INT_DMA_INTR_2 = 26, /*!< DMA_INTR[2] */ + GLB_DSP_ALL_INT_DMA_INTR_3 = 27, /*!< DMA_INTR[3] */ + GLB_DSP_ALL_INT_DMA_INTR_4 = 28, /*!< DMA_INTR[4] */ + GLB_DSP_ALL_INT_DMA_INTR_5 = 29, /*!< DMA_INTR[5] */ + GLB_DSP_ALL_INT_DMA_INTR_6 = 30, /*!< DMA_INTR[6] */ + GLB_DSP_ALL_INT_DMA_INTR_7 = 31, /*!< DMA_INTR[7] */ + GLB_DSP_ALL_INT_RSV32 = 32, /*!< rsv32 */ + GLB_DSP_ALL_INT_RSV33 = 33, /*!< rsv33 */ + GLB_DSP_ALL_INT_RSV34 = 34, /*!< rsv34 */ + GLB_DSP_ALL_INT_RSV35 = 35, /*!< rsv35 */ + GLB_DSP_ALL_INT_RSV36 = 36, /*!< rsv36 */ + GLB_DSP_ALL_INT_MIPI_CSI_INT = 37, /*!< mipi_csi_int */ + GLB_DSP_ALL_INT_IPC2_AP2NP_IRQ = 38, /*!< |ipc2_ap2np_irq */ + GLB_DSP_ALL_INT_RSV39 = 39, /*!< rsv39 */ + GLB_DSP_ALL_INT_MJDEC_INT = 40, /*!< mjdec_int */ + GLB_DSP_ALL_INT_DVP2BUS_IN_4 = 41, /*!< dvp2bus_int[4] */ + GLB_DSP_ALL_INT_DVP2BUS_IN_5 = 42, /*!< dvp2bus_int[5] */ + GLB_DSP_ALL_INT_DVP2BUS_IN_6 = 43, /*!< dvp2bus_int[6] */ + GLB_DSP_ALL_INT_DVP2BUS_IN_7 = 44, /*!< dvp2bus_int[7] */ + GLB_DSP_ALL_INT_DMA2D_INT_0 = 45, /*!< dma2d_int[0] */ + GLB_DSP_ALL_INT_DMA2D_INT_1 = 46, /*!< dma2d_int[1] */ + GLB_DSP_ALL_INT_DP_SOEF0_INT = 47, /*!< dp_soef0_int */ + GLB_DSP_ALL_INT_RSV48 = 48, /*!< rsv48 */ + GLB_DSP_ALL_INT_RSV49 = 49, /*!< rsv49 */ + GLB_DSP_ALL_INT_RSV50 = 50, /*!< rsv50 */ + GLB_DSP_ALL_INT_RSV51 = 51, /*!< rsv51 */ + GLB_DSP_ALL_INT_OSDDP_INT = 52, /*!< osdDP_int */ + GLB_DSP_ALL_INT_DBI_INT = 53, /*!< dbi_int */ + GLB_DSP_ALL_INT_RSV6_INT = 54, /*!< rsv6 */ + GLB_DSP_ALL_INT_OSDA_INT = 55, /*!< osdA_int */ + GLB_DSP_ALL_INT_OSDB_INT = 56, /*!< osdB_int */ + GLB_DSP_ALL_INT_OSD_PB_INT = 57, /*!< osd_pb_int */ + GLB_DSP_ALL_INT_RSV7_INT = 58, /*!< rsv7 */ + GLB_DSP_ALL_INT_MIPI_DSI_INT = 59, /*!< mipi_dsi_int */ + GLB_DSP_ALL_INT_RSV8_INT = 60, /*!< rsv8 */ + GLB_DSP_ALL_INT_MM_TIMER_IRQ2 = 61, /*!< mm_timer_irq2 */ + GLB_DSP_ALL_INT_MM_TIMER_IRQ3 = 62, /*!< mm_timer_irq3 */ + GLB_DSP_ALL_INT_MM_WDT_IRQ = 63, /*!< mm_wdt_irq */ +} GLB_DSP_ALL_INT_Type; + +/** + * @brief GLB MCU all interrupt type definition + */ +typedef enum { + GLB_MCU_ALL_INT_BMX_ERR_INT = 0, /*!< bmx_err_intmcu_dec_err_int */ + GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT = 1, /*!< bmx_timeout_intmcu_timeout_int */ + GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ = 2, /*!< ipc0_np2ap_irq */ + GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ = 3, /*!< ipc0_ap2np_irq */ + GLB_MCU_ALL_INT_AUDIO_INT = 4, /*!< audio_int */ + GLB_MCU_ALL_INT_RF_TOP_INT_0 = 5, /*!< rf_top_int[0] */ + GLB_MCU_ALL_INT_RF_TOP_INT_1 = 6, /*!< rf_top_int[1] */ + GLB_MCU_ALL_INT_LZ4_INT = 7, /*!< lz4_int */ + GLB_MCU_ALL_INT_RSV8 = 8, /*!< rsv8 */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT = 9, /*!< sec_eng_id0_gmac_int */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT = 10, /*!< sec_eng_id0_cdet_int */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT = 11, /*!< sec_eng_id0_pka_int */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT = 12, /*!< sec_eng_id0_trng_int */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT = 13, /*!< sec_eng_id0_aes_int */ + GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT = 14, /*!< sec_eng_id0_sha_int */ + GLB_MCU_ALL_INT_DMA_INTR_ALL = 15, /*!< DMA_INTR_ALL */ + GLB_MCU_ALL_INT_DMA2_INTR_ALL = 16, /*!< DMA2_INTR_ALL */ + GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1 = 17, /*!< sdh_mmc1_intsdh2pmu_wakeup_int1 */ + GLB_MCU_ALL_INT_MM_IRQ_ALL = 18, /*!< mm_irq_all */ + GLB_MCU_ALL_INT_IRTX_INT = 19, /*!< irtx_int */ + GLB_MCU_ALL_INT_IRRX_INT = 20, /*!< irrx_int */ + GLB_MCU_ALL_INT_USB_INT = 21, /*!< usb_int */ + GLB_MCU_ALL_INT_AUPDM_INT = 22, /*!< aupdm_int */ + GLB_MCU_ALL_INT_SF_CTRL_ID0_INT = 23, /*!< sf_ctrl_id0_int */ + GLB_MCU_ALL_INT_EMAC_INT = 24, /*!< emac_int */ + GLB_MCU_ALL_INT_GPADC_DMA_INT = 25, /*!< gpadc_dma_int */ + GLB_MCU_ALL_INT_EFUSE_INT = 26, /*!< efuse_int */ + GLB_MCU_ALL_INT_SPI_0_INT = 27, /*!< spi_0_int */ + GLB_MCU_ALL_INT_UART_IRQ = 28, /*!< uart_irq */ + GLB_MCU_ALL_INT_UART1_IRQ = 29, /*!< uart1_irq */ + GLB_MCU_ALL_INT_UART2_IRQ = 30, /*!< uart2_irq */ + GLB_MCU_ALL_INT_GPIO_DMA_INT = 31, /*!< gpio_dma_int */ + GLB_MCU_ALL_INT_I2C_0_INT = 32, /*!< i2c_0_int */ + GLB_MCU_ALL_INT_PWM_INT = 33, /*!< pwm_int */ + GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ = 34, /*!< ipc1_np2ap_irq */ + GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ = 35, /*!< ipc1_ap2np_irq */ + GLB_MCU_ALL_INT_TIMER0_2_IRQ = 36, /*!< timer0_2_irq */ + GLB_MCU_ALL_INT_TIMER0_3_IRQ = 37, /*!< timer0_3_irq */ + GLB_MCU_ALL_INT_WDT0_IRQ = 38, /*!< wdt0_irq */ + GLB_MCU_ALL_INT_I2C_1_INT = 39, /*!< i2c_1_int */ + GLB_MCU_ALL_INT_I2S0_INT = 40, /*!< i2s0_int */ + GLB_MCU_ALL_INT_RSV41 = 41, /*!< rsv41 */ + GLB_MCU_ALL_INT_RSV42 = 42, /*!< rsv42 */ + GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ = 43, /*!< ana_ocp_out_to_cpu_irq[2:0] */ + GLB_MCU_ALL_INT_GPIO_IRQ = 44, /*!< gpio_irq */ + GLB_MCU_ALL_INT_DM_IRQ = 45, /*!< dm_irq */ + GLB_MCU_ALL_INT_BT_IRQ = 46, /*!< bt_irq */ + GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT = 47, /*!< m154_req_enh_ack_int */ + GLB_MCU_ALL_INT_M154_INT = 48, /*!< m154_int */ + GLB_MCU_ALL_INT_M154_AES_INT = 49, /*!< m154_aes_int */ + GLB_MCU_ALL_INT_PDS_INT = 50, /*!< pds_int */ + GLB_MCU_ALL_INT_HBN_IRQ_OUT_0 = 51, /*!< hbn_irq_out[0] */ + GLB_MCU_ALL_INT_HBN_IRQ_OUT_1 = 52, /*!< hbn_irq_out[1] */ + GLB_MCU_ALL_INT_BOR_OUT = 53, /*!< bor_out */ + GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N = 54, /*!< wifi_to_cpu_irq_n */ + GLB_MCU_ALL_INT_BZ_PHY_INT = 55, /*!< bz_phy_int */ + GLB_MCU_ALL_INT_BLE_INT = 56, /*!< ble_int */ + GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER = 57, /*!< mac_int_tx_rx_timer */ + GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC = 58, /*!< mac_int_tx_rx_misc */ + GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER = 59, /*!< mac_int_rx_trigger */ + GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER = 60, /*!< mac_int_tx_trigger */ + GLB_MCU_ALL_INT_MAC_INT_GEN = 61, /*!< mac_int_gen */ + GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER = 62, /*!< mac_int_prot_trigger */ + GLB_MCU_ALL_INT_WIFI_IPC = 63, /*!< wifi_ipc */ +} GLB_MCU_ALL_INT_Type; + +/** + * @brief GLB LP all interrupt type definition + */ +typedef enum { + GLB_LP_ALL_INT_BMX_ERR_INT = 0, /*!< bmx_err_int */ + GLB_LP_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT = 1, /*!< bmx_timeout_intmcu_timeout_int */ + GLB_LP_ALL_INT_IPC0_NP2AP_IRQ = 2, /*!< ipc0_np2ap_irq */ + GLB_LP_ALL_INT_IPC0_AP2NP_IRQ = 3, /*!< ipc0_ap2np_irq */ + GLB_LP_ALL_INT_AUDIO_INT = 4, /*!< audio_int */ + GLB_LP_ALL_INT_RF_TOP_INT_0 = 5, /*!< rf_top_int[0] */ + GLB_LP_ALL_INT_RF_TOP_INT_1 = 6, /*!< rf_top_int[1] */ + GLB_LP_ALL_INT_LZ4_INT = 7, /*!< lz4_int */ + GLB_LP_ALL_INT_RSV8 = 8, /*!< rsv8 */ + GLB_LP_ALL_INT_SEC_ENG_ID0_GMAC_INT = 9, /*!< sec_eng_id0_gmac_int */ + GLB_LP_ALL_INT_SEC_ENG_ID0_CDET_INT = 10, /*!< sec_eng_id0_cdet_int */ + GLB_LP_ALL_INT_SEC_ENG_ID0_PKA_INT = 11, /*!< sec_eng_id0_pka_int */ + GLB_LP_ALL_INT_SEC_ENG_ID0_TRNG_INT = 12, /*!< sec_eng_id0_trng_int */ + GLB_LP_ALL_INT_SEC_ENG_ID0_AES_INT = 13, /*!< sec_eng_id0_aes_int */ + GLB_LP_ALL_INT_SEC_ENG_ID0_SHA_INT = 14, /*!< sec_eng_id0_sha_int */ + GLB_LP_ALL_INT_DMA_INTR_ALL = 15, /*!< DMA_INTR_ALL */ + GLB_LP_ALL_INT_DMA2_INTR_ALL = 16, /*!< DMA2_INTR_ALL */ + GLB_LP_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1 = 17, /*!< sdh_mmc1_intsdh2pmu_wakeup_int1 */ + GLB_LP_ALL_INT_MM_IRQ_ALL = 18, /*!< mm_irq_all */ + GLB_LP_ALL_INT_IRTX_INT = 19, /*!< irtx_int */ + GLB_LP_ALL_INT_IRRX_INT = 20, /*!< irrx_int */ + GLB_LP_ALL_INT_USB_INT = 21, /*!< usb_int */ + GLB_LP_ALL_INT_AUPDM_INT = 22, /*!< aupdm_int */ + GLB_LP_ALL_INT_SF_CTRL_ID0_INT = 23, /*!< sf_ctrl_id0_int */ + GLB_LP_ALL_INT_EMAC_INT = 24, /*!< emac_int */ + GLB_LP_ALL_INT_GPADC_DMA_INT = 25, /*!< gpadc_dma_int */ + GLB_LP_ALL_INT_EFUSE_INT = 26, /*!< efuse_int */ + GLB_LP_ALL_INT_SPI_0_INT = 27, /*!< spi_0_int */ + GLB_LP_ALL_INT_UART_IRQ = 28, /*!< uart_irq */ + GLB_LP_ALL_INT_UART1_IRQ = 29, /*!< uart1_irq */ + GLB_LP_ALL_INT_UART2_IRQ = 30, /*!< uart2_irq */ + GLB_LP_ALL_INT_GPIO_DMA_INT = 31, /*!< gpio_dma_int */ + GLB_LP_ALL_INT_I2C_0_INT = 32, /*!< i2c_0_int */ + GLB_LP_ALL_INT_PWM_INT = 33, /*!< pwm_int */ + GLB_LP_ALL_INT_IPC1_NP2AP_IRQ = 34, /*!< ipc1_np2ap_irq */ + GLB_LP_ALL_INT_IPC1_AP2NP_IRQ = 35, /*!< ipc1_ap2np_irq */ + GLB_LP_ALL_INT_TIMER0_2_IRQ = 36, /*!< timer0_2_irq */ + GLB_LP_ALL_INT_TIMER0_3_IRQ = 37, /*!< timer0_3_irq */ + GLB_LP_ALL_INT_WDT0_IRQ = 38, /*!< wdt0_irq */ + GLB_LP_ALL_INT_I2C_1_INT = 39, /*!< i2c_1_int */ + GLB_LP_ALL_INT_I2S0_INT = 40, /*!< i2s0_int */ + GLB_LP_ALL_INT_RSV41 = 41, /*!< rsv41 */ + GLB_LP_ALL_INT_RSV42 = 42, /*!< rsv42 */ + GLB_LP_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ = 43, /*!< ana_ocp_out_to_cpu_irq[2:0] */ + GLB_LP_ALL_INT_GPIO_IRQ = 44, /*!< gpio_irq */ + GLB_LP_ALL_INT_DM_IRQ = 45, /*!< dm_irq */ + GLB_LP_ALL_INT_BT_IRQ = 46, /*!< bt_irq */ + GLB_LP_ALL_INT_M154_REQ_ENH_ACK_INT = 47, /*!< m154_req_enh_ack_int */ + GLB_LP_ALL_INT_M154_INT = 48, /*!< m154_int */ + GLB_LP_ALL_INT_M154_AES_INT = 49, /*!< m154_aes_int */ + GLB_LP_ALL_INT_PDS_INT = 50, /*!< pds_int */ + GLB_LP_ALL_INT_HBN_IRQ_OUT_0 = 51, /*!< hbn_irq_out[0] */ + GLB_LP_ALL_INT_HBN_IRQ_OUT_1 = 52, /*!< hbn_irq_out[1] */ + GLB_LP_ALL_INT_BOR_OUT = 53, /*!< bor_out */ + GLB_LP_ALL_INT_WIFI_TO_CPU_IRQ_N = 54, /*!< wifi_to_cpu_irq_n */ + GLB_LP_ALL_INT_BZ_PHY_INT = 55, /*!< bz_phy_int */ + GLB_LP_ALL_INT_BLE_INT = 56, /*!< ble_int */ + GLB_LP_ALL_INT_MAC_INT_TX_RX_TIMER = 57, /*!< mac_int_tx_rx_timer */ + GLB_LP_ALL_INT_MAC_INT_TX_RX_MISC = 58, /*!< mac_int_tx_rx_misc */ + GLB_LP_ALL_INT_MAC_INT_RX_TRIGGER = 59, /*!< mac_int_rx_trigger */ + GLB_LP_ALL_INT_MAC_INT_TX_TRIGGER = 60, /*!< mac_int_tx_trigger */ + GLB_LP_ALL_INT_MAC_INT_GEN = 61, /*!< mac_int_gen */ + GLB_LP_ALL_INT_MAC_INT_PROT_TRIGGER = 62, /*!< mac_int_prot_trigger */ + GLB_LP_ALL_INT_WIFI_IPC = 63, /*!< wifi_ipc */ +} GLB_LP_ALL_INT_Type; + +/** + * @brief GLB dsp muxpll 320M clock type definition + */ +typedef enum { + GLB_DSP_MUXPLL_SEL_WIFIPLL_320M, /*!< dsp muxpll select wifipll 320M */ + GLB_DSP_MUXPLL_SEL_AUPLL_DIV1, /*!< dsp muxpll select aupll div1 */ +} GLB_DSP_MUXPLL_320M_CLK_SEL_Type; + +/** + * @brief GLB dsp muxpll 240M clock type definition + */ +typedef enum { + GLB_DSP_MUXPLL_SEL_WIFIPLL_240M, /*!< dsp muxpll select wifipll 240M */ + GLB_DSP_MUXPLL_SEL_AUPLL_DIV2, /*!< dsp muxpll select aupll div2 */ +} GLB_DSP_MUXPLL_240M_CLK_SEL_Type; + +/** + * @brief GLB dsp muxpll 160M clock type definition + */ +typedef enum { + GLB_DSP_MUXPLL_SEL_WIFIPLL_160M, /*!< dsp muxpll select wifipll 160M */ + GLB_DSP_MUXPLL_SEL_CPUPLL_160M, /*!< dsp muxpll select cpupll 160M */ +} GLB_DSP_MUXPLL_160M_CLK_SEL_Type; + +/** + * @brief GLB mcu muxpll 160M clock type definition + */ +typedef enum { + GLB_MCU_MUXPLL_SEL_WIFIPLL_160M, /*!< mcu muxpll select wifipll 160M */ + GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_160M, /*!< mcu muxpll select top cpupll 160M */ + GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2, /*!< mcu muxpll select top aupll div2 */ + GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5, /*!< mcu muxpll select aupll div2p5 */ +} GLB_MCU_MUXPLL_160M_CLK_SEL_Type; + +/** + * @brief GLB mcu muxpll 80M clock type definition + */ +typedef enum { + GLB_MCU_MUXPLL_SEL_WIFIPLL_80M, /*!< mcu muxpll select wifipll 80M */ + GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_80M, /*!< mcu muxpll select top cpupll 80M */ + GLB_MCU_MUXPLL_SEL_AUPLL_DIV5, /*!< mcu muxpll select aupll div5 */ + GLB_MCU_MUXPLL_SEL_AUPLL_DIV6, /*!< mcu muxpll select aupll div6 */ +} GLB_MCU_MUXPLL_80M_CLK_SEL_Type; + +/** + * @brief GLB pll clock gate type definition + */ +typedef enum { + GLB_PLL_CGEN_MM_WIFIPLL_160M, /*!< pll cgen mm wifipll 160m */ + GLB_PLL_CGEN_MM_WIFIPLL_240M, /*!< pll cgen mm wifipll 240m */ + GLB_PLL_CGEN_MM_WIFIPLL_320M, /*!< pll cgen mm wifipll 320m */ + GLB_PLL_CGEN_MM_AUPLL_DIV1, /*!< pll cgen mm aupll div1 */ + GLB_PLL_CGEN_MM_AUPLL_DIV2, /*!< pll cgen mm aupll div2 */ + GLB_PLL_CGEN_EMI_CPUPLL_400M, /*!< pll cgen emi cpupll 400m */ + GLB_PLL_CGEN_EMI_CPUPLL_200M, /*!< pll cgen emi cpupll 200m */ + GLB_PLL_CGEN_EMI_WIFIPLL_320M, /*!< pll cgen emi wifipll 320m */ + GLB_PLL_CGEN_EMI_AUPLL_DIV1, /*!< pll cgen emi aupll div1 */ + GLB_PLL_CGEN_TOP_CPUPLL_80M, /*!< pll cgen top cpupll 80m */ + GLB_PLL_CGEN_TOP_CPUPLL_100M, /*!< pll cgen top cpupll 100m */ + GLB_PLL_CGEN_TOP_CPUPLL_160M, /*!< pll cgen top cpupll 160m */ + GLB_PLL_CGEN_TOP_CPUPLL_400M, /*!< pll cgen top cpupll 400m */ + GLB_PLL_CGEN_TOP_WIFIPLL_240M, /*!< pll cgen top wifipll 240m */ + GLB_PLL_CGEN_TOP_WIFIPLL_320M, /*!< pll cgen top wifipll 320m */ + GLB_PLL_CGEN_TOP_AUPLL_DIV2, /*!< pll cgen top aupll div2 */ + GLB_PLL_CGEN_TOP_AUPLL_DIV1, /*!< pll cgen top aupll div1 */ +} GLB_PLL_CGEN_Type; + +/** + * @brief GLB mcu system clock type definition + */ +typedef enum { + GLB_MCU_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_MCU_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_MCU_SYS_CLK_CPUPLL_400M, /*!< use CPUPLL output 400M as system clock */ + GLB_MCU_SYS_CLK_WIFIPLL_240M, /*!< use WIFIPLL output 240M as system clock */ + GLB_MCU_SYS_CLK_WIFIPLL_320M, /*!< use WIFIPLL output 320M as system clock */ +} GLB_MCU_SYS_CLK_Type; + +/** + * @brief GLB dsp system clock type definition + */ +typedef enum { + GLB_DSP_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_DSP_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_DSP_SYS_CLK_MM_WIFIPLL_240M, /*!< use WIFIPLL 240M as system clock */ + GLB_DSP_SYS_CLK_MM_WIFIPLL_320M, /*!< use WIFIPLL 320M as system clock */ + GLB_DSP_SYS_CLK_CPUPLL_400M, /*!< use CPUPLL output 400M as system clock */ +} GLB_DSP_SYS_CLK_Type; + +/** + * @brief GLB dsp pbus clock type definition + */ +typedef enum { + GLB_DSP_SYS_PBCLK_RC32M, /*!< use rc32m as pbus clock */ + GLB_DSP_SYS_PBCLK_XTAL, /*!< use xtal as pbus clock */ + GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M, /*!< use mm_wifipll_160m_clk as pbus clock */ + GLB_DSP_SYS_PBCLK_CPUPLL_160M, /*!< use cpupll_160m_clk as pbus clock */ + GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M, /*!< use mm_wifipll_240m_clk as pbus clock */ +} GLB_DSP_SYS_PBCLK_Type; + +/** + * @brief GLB dsp system clock type definition + */ +typedef enum { + GLB_PLL_REFCLK_XTAL = 0, /*!< use XTAL as pll ref clock */ + GLB_PLL_REFCLK_RC32M = 3, /*!< use RC32M as pll ref clock */ +} GLB_PLL_REF_CLK_Type; + +typedef struct { + uint8_t clkpllRefdivRatio; /*!< xxx pll_refdiv_ratio */ + uint8_t clkpllIntFracSw; /*!< xxx pll_int_frac_sw */ + uint8_t clkpllIcp1u; /*!< xxx pll_icp_1u */ + uint8_t clkpllIcp5u; /*!< xxx pll_icp_5u */ + uint8_t clkpllRz; /*!< xxx pll_rz */ + uint8_t clkpllCz; /*!< xxx pll_cz */ + uint8_t clkpllC3; /*!< xxx pll_c3 */ + uint8_t clkpllR4Short; /*!< xxx pll_r4_short */ + uint8_t clkpllC4En; /*!< xxx pll_r4_en */ + uint8_t clkpllSelSampleClk; /*!< xxx pll_sel_sample_clk */ + uint8_t clkpllVcoSpeed; /*!< xxx pll_vco_speed */ + uint8_t clkpllSdmCtrlHw; /*!< xxx pll_sdm_ctrl_hw */ + uint8_t clkpllSdmBypass; /*!< xxx pll_sdm_bypass */ +} GLB_WAC_PLL_CFG_BASIC_Type; + +typedef struct { + const GLB_WAC_PLL_CFG_BASIC_Type *const basicCfg; /*!< pll basic configuration */ + uint32_t clkpllSdmin; /*!< pll sdmin value */ +} GLB_WAC_PLL_Cfg_Type; + +typedef struct { + uint8_t clkpllRefdivRatio; /*!< xxx pll_refdiv_ratio */ + uint8_t clkpllSelSampleClk; /*!< xxx pll_sel_sample_clk */ + uint8_t clkpllVcoSpeed; /*!< xxx pll_vco_speed */ + uint8_t clkpllEvenDivEn; /*!< xxx pll_even_div_en */ + uint8_t clkpllEvenDivRatio; /*!< xxx pll_even_div_ratio */ +} GLB_MU_PLL_CFG_BASIC_Type; + +typedef struct { + const GLB_MU_PLL_CFG_BASIC_Type *const basicCfg; /*!< pll basic configuration */ + uint32_t clkpllSdmin; /*!< pll sdmin value */ +} GLB_MU_PLL_Cfg_Type; + +/** + * @brief GLB CAM clock type definition + */ +typedef enum { + GLB_CAM_CLK_XCLK, /*!< Select XCLK as CAM clock */ + GLB_CAM_CLK_WIFIPLL_96M, /*!< Select WIFIPLL_96M as CAM clock */ + GLB_CAM_CLK_CPUPLL_100M, /*!< Select CPUPLL_96M as CAM clock */ +} GLB_CAM_CLK_Type; + +/** + * @brief GLB SDH clock type definition + */ +typedef enum { + GLB_SDH_CLK_WIFIPLL_96M, /*!< Select WIFIPLL_96M as SDH clock */ + GLB_SDH_CLK_CPUPLL_100M, /*!< Select CPUPLL_100M as SDH clock */ +} GLB_SDH_CLK_Type; + +/** + * @brief GLB UART sig swap group type definition + */ +typedef enum { + GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, /*!< SWAP UART SIG GROUP GPIO0 - GPIO11 */ + GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, /*!< SWAP UART SIG GROUP GPIO12 - GPIO23 */ + GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, /*!< SWAP UART SIG GROUP GPIO24 - GPIO35 */ + GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, /*!< SWAP UART SIG GROUP GPIO36 - GPIO45 */ +} GLB_UART_SIG_SWAP_GRP_Type; + +/** + * @brief GLB I2S output ref clock type definition + */ +typedef enum { + GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */ + GLB_I2S_OUT_REF_CLK_SRC, /*!< output reference clock on I2S_0 ref_clock port */ +} GLB_I2S_OUT_REF_CLK_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA0_CLK_CH0, /*!< DMA0 clock ID:channel 0 */ + GLB_DMA0_CLK_CH1, /*!< DMA0 clock ID:channel 1 */ + GLB_DMA0_CLK_CH2, /*!< DMA0 clock ID:channel 2 */ + GLB_DMA0_CLK_CH3, /*!< DMA0 clock ID:channel 3 */ + GLB_DMA0_CLK_CH4, /*!< DMA0 clock ID:channel 4 */ + GLB_DMA0_CLK_CH5, /*!< DMA0 clock ID:channel 5 */ + GLB_DMA0_CLK_CH6, /*!< DMA0 clock ID:channel 6 */ + GLB_DMA0_CLK_CH7, /*!< DMA0 clock ID:channel 7 */ + GLB_DMA1_CLK_CH0, /*!< DMA1 clock ID:channel 0 */ + GLB_DMA1_CLK_CH1, /*!< DMA1 clock ID:channel 1 */ + GLB_DMA1_CLK_CH2, /*!< DMA1 clock ID:channel 2 */ + GLB_DMA1_CLK_CH3, /*!< DMA1 clock ID:channel 3 */ +} GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB peripheral DMA type definition + */ +typedef enum { + GLB_PERI_DMA_UART0_RX = 0, /*!< uart_rx */ + GLB_PERI_DMA_UART0_TX = 1, /*!< uart_tx */ + GLB_PERI_DMA_UART1_RX = 2, /*!< uart1_rx */ + GLB_PERI_DMA_UART1_TX = 3, /*!< uart1_tx */ + GLB_PERI_DMA_UART2_RX = 4, /*!< uart2_rx */ + GLB_PERI_DMA_UART2_TX = 5, /*!< uart2_tx */ + GLB_PERI_DMA_I2C_0_RX = 6, /*!< i2c_0_rx */ + GLB_PERI_DMA_I2C_0_TX = 7, /*!< i2c_0_tx */ + GLB_PERI_DMA_IRTX_TX = 8, /*!< irtx_tx */ + GLB_PERI_DMA_GPIO_TX = 9, /*!< gpio_tx */ + GLB_PERI_DMA_SPI_RX = 10, /*!< spi_rx */ + GLB_PERI_DMA_SPI_TX = 11, /*!< spi_tx */ + GLB_PERI_DMA_AUDIO_RX = 12, /*!< audio_rx */ + GLB_PERI_DMA_AUDIO_TX = 13, /*!< audio_tx */ + GLB_PERI_DMA_I2C_1_RX = 14, /*!< i2c_1_rx */ + GLB_PERI_DMA_I2C_1_TX = 15, /*!< i2c_1_tx */ + GLB_PERI_DMA_I2S_0_RX = 16, /*!< i2s_0_rx */ + GLB_PERI_DMA_I2S_0_TX = 17, /*!< i2s_0_tx */ + GLB_PERI_DMA_PDM_RX = 18, /*!< pdm_rx */ + GLB_PERI_DMA_PADC = 19, /*!< padc */ + GLB_PERI_DMA_GAUGE = 20, /*!< gauge */ + GLB_PERI_DMA_GPADC = 22, /*!< gpadc */ + GLB_PERI_DMA_GPDAC_TX = 23, /*!< gpdac_tx */ +} GLB_PERI_DMA_Type; + +/** + * @brief GLB DMA CN selection type definition + */ +typedef enum { + GLB_PERI_DMA_CN_SEL_DMA0 = 0, /*!< peripheral DMA channel select DMA0 */ + GLB_PERI_DMA_CN_SEL_DMA1 = 1, /*!< peripheral DMA channel select DMA1 */ +} GLB_PERI_DMA_CN_SEL_Type; + +/** + * @brief GLB clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +} GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_120M_WIFIPLL, /*!< Select WIFIPLL 120M as flash clock */ + GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */ + GLB_SFLASH_CLK_100M_CPUPLL, /*!< Select CPUPLL 100M as flash clock */ + GLB_SFLASH_CLK_80M_MUXPLL, /*!< Select MUXPLL 80M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_96M_WIFIPLL, /*!< Select WIFIPLL 96M as flash clock */ +} GLB_SFLASH_CLK_Type; + +/** + * @brief GLB I2C clock type definition + */ +typedef enum { + GLB_I2C_CLK_BCLK, /*!< Select bus clk as I2C clock */ + GLB_I2C_CLK_XCLK, /*!< Select xclk as I2C clock */ +} GLB_I2C_CLK_Type; + +/** + * @brief GLB SPI clock type definition + */ +typedef enum { + GLB_SPI_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as SPI clock */ + GLB_SPI_CLK_XCLK, /*!< Select xclk as SPI clock */ +} GLB_SPI_CLK_Type; + +/** + * @brief GLB PWM1 io type definition + */ +typedef enum { + GLB_PWM1_IO_SINGLE_END, /*!< Select pwm1 io single end */ + GLB_PWM1_IO_DIFF_END, /*!< Select pwm1 io differential end for BLDC */ +} GLB_PWM1_IO_SEL_Type; + +/** + * @brief GLB PWM2 io type definition + */ +typedef enum { + GLB_PWM2_IO_SINGLE_END, /*!< Select pwm2 io single end */ + GLB_PWM2_IO_SINGLE_END_BLDC, /*!< Select pwm2 io single end BLDC */ +} GLB_PWM2_IO_SEL_Type; + +/** + * @brief GLB PDM io type definition + */ +typedef enum { + GLB_PDM_IO_SEL_AUDIO_TOP, /*!< Select audio_top PDM */ + GLB_PDM_IO_SEL_AUPDM_TOP, /*!< Select aupdm_top PDM */ +} GLB_PDM_IO_SEL_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +} GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB AHB software type definition + */ +typedef enum { + GLB_AHB_MCU_SW_RSV0 = 0, + GLB_AHB_MCU_SW_RSV1 = 1, + GLB_AHB_MCU_SW_WIFI = 4, + GLB_AHB_MCU_SW_BTDM = 8, + GLB_AHB_MCU_SW_ZIGBEE = 9, + GLB_AHB_MCU_SW_BLE2 = 10, + GLB_AHB_MCU_SW_ZIGBEE2 = 11, + GLB_AHB_MCU_SW_EMI_MISC = 16, + GLB_AHB_MCU_SW_PSRAM0_CTRL = 17, + GLB_AHB_MCU_SW_PSRAM1_CTRL = 18, + GLB_AHB_MCU_SW_USB_EMAC = 19, + GLB_AHB_MCU_SW_RSV20 = 20, + GLB_AHB_MCU_SW_AUDIO = 21, + GLB_AHB_MCU_SW_SDH = 22, + GLB_AHB_MCU_SW_RSV23 = 23, + GLB_AHB_MCU_SW_DMA2 = 24, + GLB_AHB_MCU_SW_GLB = 32, + GLB_AHB_MCU_SW_MIX = 33, + GLB_AHB_MCU_SW_GPIP = 34, + GLB_AHB_MCU_SW_SEC_DBG = 35, + GLB_AHB_MCU_SW_SEC_ENG = 36, + GLB_AHB_MCU_SW_TZ1 = 37, + GLB_AHB_MCU_SW_TZ2 = 38, + GLB_AHB_MCU_SW_EFUSE = 39, + GLB_AHB_MCU_SW_CCI = 40, + GLB_AHB_MCU_SW_MCU_PERI_BUS = 41, + GLB_AHB_MCU_SW_RSV42 = 42, + GLB_AHB_MCU_SW_SF = 43, + GLB_AHB_MCU_SW_DMA = 44, + GLB_AHB_MCU_SW_SDU = 45, + GLB_AHB_MCU_SW_PDS = 46, + GLB_AHB_MCU_SW_RSV47 = 47, + GLB_AHB_MCU_SW_UART0 = 48, + GLB_AHB_MCU_SW_UART1 = 49, + GLB_AHB_MCU_SW_SPI = 50, + GLB_AHB_MCU_SW_I2C = 51, + GLB_AHB_MCU_SW_PWM = 52, + GLB_AHB_MCU_SW_TIMER = 53, + GLB_AHB_MCU_SW_IR_REMOTE = 54, + GLB_AHB_MCU_SW_CHECKSUM = 55, + GLB_AHB_MCU_SW_IPC = 56, + GLB_AHB_MCU_SW_I2C1 = 57, + GLB_AHB_MCU_SW_UART2 = 58, + GLB_AHB_MCU_SW_I2S = 59, + GLB_AHB_MCU_SW_AUPDM = 60, + GLB_AHB_MCU_SW_LZ4 = 61, + GLB_AHB_MCU_SW_RSV62 = 62, + GLB_AHB_MCU_SW_RSV63 = 63, + GLB_AHB_MCU_SW_PWRON_RST = 64, + GLB_AHB_MCU_SW_CPU_RESET = 65, + GLB_AHB_MCU_SW_SYS_RESET = 66, + GLB_AHB_MCU_SW_PICO_RESET = 67, + GLB_AHB_MCU_SW_CPU2_RESET = 68, + GLB_AHB_MCU_SW_CHIP_RESET = 69, + GLB_AHB_MCU_SW_WL_WDT_RESET_MM_EN = 70, + GLB_AHB_MCU_SW_MMWDT2WL_RST_MSK = 71, +} GLB_AHB_MCU_SW_Type; + +/** + * @brief GLB AHB software type definition + */ +typedef enum { + GLB_AHB_DSP_SW_REG_CTRL_SYS_RESET = 0, + GLB_AHB_DSP_SW_REG_CTRL_PWRON_RST = 2, + GLB_AHB_DSP_SW_REG_CTRL_MMCPU0_RESET = 8, + GLB_AHB_DSP_SW_SWRST_MM_MISC = 32, + GLB_AHB_DSP_SW_SWRST_DMA = 33, + GLB_AHB_DSP_SW_SWRST_UART0 = 34, + GLB_AHB_DSP_SW_SWRST_I2C0 = 35, + GLB_AHB_DSP_SW_SWRST_I2C1 = 36, + GLB_AHB_DSP_SW_SWRST_IPC = 37, + GLB_AHB_DSP_SW_SWRST_DMA2D = 38, + GLB_AHB_DSP_SW_SWRST_SPI = 40, + GLB_AHB_DSP_SW_SWRST_TIMER = 41, + GLB_AHB_DSP_SW_SWRST_I2S0 = 42, + GLB_AHB_DSP_SW_SWRST_I2S1 = 43, + GLB_AHB_DSP_SW_SWRST_PDM0 = 44, + GLB_AHB_DSP_SW_SWRST_PDM1 = 45, + GLB_AHB_DSP_SW_SWRST_PUHS = 47, + GLB_AHB_DSP_SW_SWRST_SUB_MISC = 64, + GLB_AHB_DSP_SW_SWRST_SUB_MAIN = 65, + GLB_AHB_DSP_SW_SWRST_SUB_TSRC = 66, + GLB_AHB_DSP_SW_SWRST_DP_TSRC = 67, + GLB_AHB_DSP_SW_SWRST_NR3D_CTRL = 68, + GLB_AHB_DSP_SW_SWRST_DVP2BUSA = 69, + GLB_AHB_DSP_SW_SWRST_DVP2BUSB = 70, + GLB_AHB_DSP_SW_SWRST_DVP2BUSC = 71, + GLB_AHB_DSP_SW_SWRST_DVP2BUSD = 72, + GLB_AHB_DSP_SW_SWRST_MIPI = 73, + GLB_AHB_DSP_SW_SWRST_SUB_REG = 80, + GLB_AHB_DSP_SW_SWRST_DVP2BUSE = 81, + GLB_AHB_DSP_SW_SWRST_DVP2BUSF = 82, + GLB_AHB_DSP_SW_SWRST_DVP2BUSG = 83, + GLB_AHB_DSP_SW_SWRST_DVP2BUSH = 84, + GLB_AHB_DSP_SW_SWRST_CODEC_MISC = 96, + GLB_AHB_DSP_SW_SWRST_MJPEG = 97, + GLB_AHB_DSP_SW_SWRST_H264 = 98, + GLB_AHB_DSP_SW_SWRST_MJPEG_DEC = 99, + GLB_AHB_DSP_SW_SWRST_CNN = 100, + GLB_AHB_DSP_SW_SWRST_VRAM = 112, + GLB_AHB_DSP_SW_RG_IS_RST_N = 128, +} GLB_AHB_DSP_SW_Type; + +/** + * @brief GLB dis reset type definition + */ +typedef enum { + GLB_DISRST_GPIP = 2, + GLB_DISRST_SEC_ENG = 4, + GLB_DISRST_CCI = 8, + GLB_DISRST_SF = 11, + GLB_DISRST_UART0 = 16, + GLB_DISRST_UART1 = 17, + GLB_DISRST_SPI = 18, + GLB_DISRST_I2C0 = 19, + GLB_DISRST_PWM = 20, + GLB_DISRST_TIMER = 21, + GLB_DISRST_IR_REMOTE = 22, + GLB_DISRST_CHECKSUM = 23, + GLB_DISRST_IPC = 24, + GLB_DISRST_I2C1 = 25, + GLB_DISRST_UART2 = 26, +} GLB_DISRST_Type; + +/** + * @brief GLB PKA clock type definition + */ +typedef enum { + GLB_PKA_CLK_MCU_BCLK, /*!< Select MCU_BCLK as PKA clock */ + GLB_PKA_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as PKA clock */ +} GLB_PKA_CLK_Type; + +/** + * @brief GLB MCU software system reset type definition + */ +typedef enum { + GLB_MCU_SW_SYSTEM_CTRL_MCU = 1, /*!< mcu reset */ + GLB_MCU_SW_SYSTEM_CTRL_LP = 3, /*!< lp reset */ +} GLB_MCU_SW_SYSTEM_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_ROUND_ROBIN = 0, /*!< 0->round-robin */ + BMX_ARB_FIX = 1, /*!< 1->fix */ +} BMX_ARB_Type; + +/** + * @brief BMX latch type definition + */ +typedef enum { + BMX_LATCH_FIRST_ERROR = 0, /*!< 0->Latch first error */ + BMX_LATCH_LAST_ERROR = 1, /*!< 1->Latch last error */ +} BMX_LATCH_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct { + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ +} BMX_TO_Cfg_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +} BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +} BMX_TO_INT_Type; + +/** + * @brief GLB eth ref clock out type definition + */ +typedef enum { + GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */ + GLB_ETH_REF_CLK_OUT_INSIDE_50M, /*!< select inside 50MHz RMII ref clock */ +} GLB_ETH_REF_CLK_OUT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_WRAM160KB_EM0KB, /*!< WRAM_160KB EM_0KB */ + GLB_WRAM144KB_EM16KB, /*!< WRAM_144KB EM_16KB */ + GLB_WRAM128KB_EM32KB, /*!< WRAM_128KB EM_32KB */ + GLB_WRAM112KB_EM48KB, /*!< WRAM_112KB EM_48KB */ + GLB_WRAM96KB_EM64KB, /*!< WRAM_96KB EM_64KB */ +} GLB_EM_Type; + +/** + * @brief GLB ADC clock type definition + */ +typedef enum { + GLB_ADC_CLK_AUPLL, /*!< use AUPLL as ADC clock */ + GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ +} GLB_ADC_CLK_Type; + +/** + * @brief GLB DAC clock type definition + */ +typedef enum { + GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */ + GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */ +} GLB_DAC_CLK_Type; + +/** + * @brief GLB chip clock input output type definition + */ +/** + * @brief GLB chip clock out 0 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_0_CAM_REF_CLK = 0, /*!< cam_ref_clk */ + GLB_CHIP_CLK_OUT_0_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */ + GLB_CHIP_CLK_OUT_0_CLK_AUDIO_ADC = 2, /*!< clk_adc */ + GLB_CHIP_CLK_OUT_0_CLK_AUDIO_DAC = 3, /*!< clk_dac */ +} GLB_CHIP_CLK_OUT_0_Type; + +/** + * @brief GLB chip clock out 1 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_1_CAM_REF_CLK = 0, /*!< no chip clock out */ + GLB_CHIP_CLK_OUT_1_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */ + GLB_CHIP_CLK_OUT_1_CLK_AUDIO_ADC = 2, /*!< clk_adc_in_128fs */ + GLB_CHIP_CLK_OUT_1_CLK_AUDIO_DAC = 3, /*!< clk_dac_in_128fs */ +} GLB_CHIP_CLK_OUT_1_Type; + +/** + * @brief GLB chip clock out 2 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_2_CAM_REF_CLK = 0, /*!< cam_ref_clk */ + GLB_CHIP_CLK_OUT_2_I2S_REF_CLK = 1, /*!< i2s_ref_clk */ + GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK = 2, /*!< ana_xtal_clk */ + GLB_CHIP_CLK_OUT_2_PLL_32M_CLK = 3, /*!< pll_32m_clk */ +} GLB_CHIP_CLK_OUT_2_Type; + +/** + * @brief GLB chip clock out 3 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_3_CAM_REF_CLK = 0, /*!< no chip clock out */ + GLB_CHIP_CLK_OUT_3_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */ + GLB_CHIP_CLK_OUT_3_NONE = 2, /*!< no clock out */ + GLB_CHIP_CLK_OUT_3_PLL_48M_CLK = 3, /*!< pll_48m_clk */ +} GLB_CHIP_CLK_OUT_3_Type; + +/** + * @brief GLB CSI DSI clock source select type definition + */ +typedef enum { + GLB_CSI_DSI_CLK_SEL_XTAL_CLK, /*!< xtal_clk */ + GLB_CSI_DSI_CLK_SEL_CPUPLL_DIV10, /*!< cpupll_div10 */ +} GLB_CSI_DSI_CLK_SEL_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_WIFIPLL_32M, /*!< select WIFIPLL 32M as DIG clock source */ + GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ + GLB_DIG_CLK_AUPLL, /*!< select AUPLL as DIG clock source */ +} GLB_DIG_CLK_Type; + +/** + * @brief GLB 512K clock out select type definition + */ +typedef enum { + GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */ + GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */ + GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */ +} GLB_512K_CLK_OUT_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +} GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART2 IO selection type definition + */ +typedef enum { + GLB_UART2_IO_SEL_UART2, /*!< Select UART2 function */ + GLB_UART2_IO_SEL_ISO11898, /*!< Select ISO11898 function */ +} GLB_UART2_IO_SEL_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ + GLB_UART_SIG_4, /*!< UART signal 4 */ + GLB_UART_SIG_5, /*!< UART signal 5 */ + GLB_UART_SIG_6, /*!< UART signal 6 */ + GLB_UART_SIG_7, /*!< UART signal 7 */ + GLB_UART_SIG_8, /*!< UART signal 8 */ + GLB_UART_SIG_9, /*!< UART signal 9 */ + GLB_UART_SIG_10, /*!< UART signal 10 */ + GLB_UART_SIG_11, /*!< UART signal 11 */ +} GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ + GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ + GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ + GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ + GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ + GLB_UART_SIG_FUN_UART2_RTS, /*!< UART funtion: UART 2 RTS */ + GLB_UART_SIG_FUN_UART2_CTS, /*!< UART funtion: UART 2 CTS */ + GLB_UART_SIG_FUN_UART2_TXD, /*!< UART funtion: UART 2 TXD */ + GLB_UART_SIG_FUN_UART2_RXD, /*!< UART funtion: UART 2 RXD */ +} GLB_UART_SIG_FUN_Type; + +/** + * @brief XTAL type definition + */ +typedef enum { + GLB_XTAL_NONE, /*!< XTAL is none */ + GLB_XTAL_24M, /*!< XTAL is 24M */ + GLB_XTAL_32M, /*!< XTAL is 32M */ + GLB_XTAL_38P4M, /*!< XTAL is 38.4M */ + GLB_XTAL_40M, /*!< XTAL is 40M */ + GLB_XTAL_26M, /*!< XTAL is 26M */ + GLB_XTAL_RC32M, /*!< XTAL is RC32M */ + GLB_XTAL_MAX, /*!< type max num */ +} GLB_XTAL_Type; + +/** + * @brief PLL power on type definition + */ +typedef enum { + GLB_PLL_NONE = 0, /*!< power on xtal and pll */ + GLB_PLL_WIFIPLL = 1, /*!< power on WIFIPLL */ + GLB_PLL_AUPLL = 2, /*!< power on AUPLL */ + GLB_PLL_CPUPLL = 4, /*!< power on CPUPLL */ + GLB_PLL_MIPIPLL = 8, /*!< power on ETHPLL */ + GLB_PLL_UHSPLL = 16, /*!< power on ETHPLL */ +} GLB_PLL_Type; + +/** + * @brief WAC PLL XTAL type definition + */ +typedef enum { + GLB_WAC_PLL_WIFIPLL, /*!< wifi pll */ + GLB_WAC_PLL_AUPLL, /*!< audio pll */ + GLB_WAC_PLL_CPUPLL, /*!< cpu pll */ +} GLB_WAC_PLL_Type; + +/** + * @brief MU PLL XTAL type definition + */ +typedef enum { + GLB_MU_PLL_MIPIPLL, /*!< mipi pll */ + GLB_MU_PLL_UHSPLL, /*!< uhs pll */ +} GLB_MU_PLL_Type; + +/** + * @brief DISP clock type definition + */ +typedef enum { + GLB_DISP_CLK_MIPIPLL_1500M, /*!< mipi pll 1500M */ +} GLB_DISP_CLK_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_PSRAM_EMI_CPUPLL_400M, /*!< emi_cpupll_400m_clk */ + GLB_PSRAM_EMI_WIFIPLL_320M, /*!< emi_wifipll_320m_clk */ + GLB_PSRAM_EMI_AUPLL_DIV1, /*!< emi_aupll_div1_clk */ +} GLB_PSRAM_PLL_Type; + +/** + * @brief GLB DSP xclk clock type definition + */ +typedef enum { + GLB_DSP_XCLK_RC32M, /*!< use RC32M as xclk clock */ + GLB_DSP_XCLK_XTAL, /*!< use XTAL as xclk clock */ +} GLB_DSP_XCLK_Type; + +/** + * @brief GLB DSP root clock type definition + */ +typedef enum { + GLB_DSP_ROOT_CLK_XCLK, /*!< use XCLK as root clock */ + GLB_DSP_ROOT_CLK_PLL, /*!< use PLL as root clock */ +} GLB_DSP_ROOT_CLK_Type; + +/** + * @brief GLB DSP pbroot clock type definition + */ +typedef enum { + GLB_DSP_PBROOT_CLK_MM_XCLK, /*!< use mm_xclk as pbroot clock */ + GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M, /*!< use mm_muxpll_160m_clk as pbroot clock */ + GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M, /*!< use mm_muxpll_240m_clk as pbroot clock */ +} GLB_DSP_PBROOT_CLK_Type; + +/** + * @brief GLB DSP PLL clock type definition + */ +typedef enum { + GLB_DSP_PLL_CLK_MUXPLL_240M, /*!< select DSP PLL output muxpll 240m as cpu clock */ + GLB_DSP_PLL_CLK_MUXPLL_320M, /*!< select DSP PLL output muxpll 320m as cpu clock */ + GLB_DSP_PLL_CLK_CPUPLL_400M, /*!< select DSP PLL output cpupll 400m as cpu clock */ +} GLB_DSP_PLL_CLK_Type; + +/** + * @brief GLB DSP UART clock type definition + */ +typedef enum { + GLB_DSP_UART_CLK_DSP_PBCLK, /*!< Select dsp pbclk as UART clock */ + GLB_DSP_UART_CLK_MUXPLL_160M, /*!< Select muxpll 160m as UART clock */ + GLB_DSP_UART_CLK_DSP_XCLK, /*!< Select xclk as UART clock */ +} GLB_DSP_UART_CLK_Type; + +/** + * @brief GLB UART clock type definition + */ +typedef enum { + GLB_UART_CLK_BCLK, /*!< Select bclk clock as UART clock */ + GLB_UART_CLK_PLL_160M, /*!< Select PLL 160M as UART clock */ +} GLB_UART_CLK_Type; + +/** + * @brief GLB DSP CNN clock type definition + */ +typedef enum { + GLB_DSP_CNN_CLK_160M, /*!< Select 160M as CNN clock */ + GLB_DSP_CNN_CLK_240M, /*!< Select 240M as CNN clock */ + GLB_DSP_CNN_CLK_320M, /*!< Select 320M as CNN clock */ +} GLB_DSP_CNN_CLK_Type; + +/** + * @brief GLB DSP DP clock type definition + */ +typedef enum { + GLB_DSP_DP_CLK_DISPLAY_PLL, /*!< Select display pll as DP clock */ + GLB_DSP_DP_CLK_DSP_XCLK, /*!< Select mm xclk as DP clock */ +} GLB_DSP_DP_CLK_Type; + +/** + * @brief GLB DSP clock type definition + */ +typedef enum { + GLB_DSP_CLK_MUXPLL_160M, /*!< Select muxpll 160M as DSP sub clock */ + GLB_DSP_CLK_MUXPLL_240M, /*!< Select muxpll 240M as DSP sub clock */ + GLB_DSP_CLK_CPUPLL_400M, /*!< Select cpupll 400M as DSP sub clock */ + GLB_DSP_CLK_DSP_XCLK, /*!< Select dsp xclk as DSP sub clock */ +} GLB_DSP_CLK_Type; + +/** + * @brief GLB DSP H264 clock type definition + */ +typedef enum { + GLB_DSP_H264_DSP_MUXPLL_160M, /*!< Select dsp muxpll 160M as SUB clock */ + GLB_DSP_H264_DSP_MUXPLL_240M, /*!< Select dsp muxpll 240M as SUB clock */ + GLB_DSP_H264_DSP_MUXPLL_320M, /*!< Select dsp muxpll 320M as SUB clock */ +} GLB_DSP_H264_CLK_Type; + +/** + * @brief GLB DSP SPI clock type definition + */ +typedef enum { + GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, /*!< Select muxpll 160M as SPI clock */ + GLB_DSP_SPI_CLK_DSP_XCLK, /*!< Select xclk as SPI clock */ +} GLB_DSP_SPI_CLK_Type; + +/** + * @brief GLB DSP I2C clock type definition + */ +typedef enum { + GLB_DSP_I2C_CLK_DSP_PBCLK, /*!< Select dsp pbclk as I2C clock */ + GLB_DSP_I2C_CLK_XCLK, /*!< Select xclk as I2C clock */ +} GLB_DSP_I2C_CLK_Type; + +/** + * @brief GLB I2S di ref clock type definition + */ +typedef enum { + GLB_I2S_DI_SEL_I2S_DI_INPUT, /*!< Select i2s_di input */ + GLB_I2S_DI_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */ +} GLB_I2S_DI_REF_CLK_Type; + +/** + * @brief GLB I2S do ref clock type definition + */ +typedef enum { + GLB_I2S_DO_SEL_I2S_DO_OUTPT, /*!< Select i2s_do output */ + GLB_I2S_DO_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */ +} GLB_I2S_DO_REF_CLK_Type; + +/** + * @brief GLB EMI clock type definition + */ +typedef enum { + GLB_EMI_CLK_MCU_PBCLK, /*!< mcu_pbclk */ + GLB_EMI_CLK_CPUPLL_200M_CLK, /*!< cpupll_200m_clk */ + GLB_EMI_CLK_WIFIPLL_320M_CLK, /*!< wifipll_320m_clk */ + GLB_EMI_CLK_CPUPLL_400M_CLK, /*!< cpupll_400m_clk */ +} GLB_EMI_CLK_Type; + +/** + * @brief GLB DSP sw system type definition + */ +typedef enum { + GLB_DSP_SW_SYSTEM_CTRL_SYS = 0, /*!< SW system reset(pulse trigger) */ + GLB_DSP_SW_SYSTEM_CTRL_PWRON = 2, /*!< SW power-on reset (pulse trigger) */ + GLB_DSP_SW_SYSTEM_CTRL_DSP0 = 8, /*!< MMCPU0 reset(pulse trigger) */ + GLB_DSP_SW_SYSTEM_CTRL_DSP1 = 9, /*!< MMCPU1 reset(pulse trigger) */ + GLB_DSP_SW_SYSTEM_CTRL_WL2MM = 15, /*!< wl2mm */ +} GLB_DSP_SW_SYSTEM_Type; + +/** + * @brief GLB DSP peripheral type definition + */ +typedef enum { + GLB_DSP_PERIPHERAL_MM_MISC = 0, /*!< mm_misc */ + GLB_DSP_PERIPHERAL_DMA = 1, /*!< dma */ + GLB_DSP_PERIPHERAL_UART0 = 2, /*!< uart0 */ + GLB_DSP_PERIPHERAL_I2C0 = 3, /*!< i2c0 */ + GLB_DSP_PERIPHERAL_IPC = 5, /*!< ipc */ + GLB_DSP_PERIPHERAL_SPI = 8, /*!< spi */ + GLB_DSP_PERIPHERAL_TIMER = 9, /*!< timer */ + GLB_DSP_PERIPHERAL_I2S0 = 10, /*!< i2s0 */ +} GLB_DSP_PERIPHERAL_Type; + +/** + * @brief GLB DSP sub type definition + */ +typedef enum { + GLB_DSP_SUB_MISC = 0, /*!< sub_misc */ + GLB_DSP_SUB_DVP2BUSA = 1, /*!< dvp2busA */ + GLB_DSP_SUB_DVP2BUSB = 2, /*!< dvp2busB */ + GLB_DSP_SUB_DVP2BUSC = 3, /*!< dvp2busC */ + GLB_DSP_SUB_OSD_DRAW = 4, /*!< osd_draw */ + GLB_DSP_SUB_DP = 5, /*!< display */ + GLB_DSP_SUB_IMG_PR = 16, /*!< img_pr scaler/yuv2rgb */ + GLB_DSP_SUB_SCLRA = 17, /*!< ScalerA */ + GLB_DSP_SUB_SCLRB = 18, /*!< ScalerB */ +} GLB_DSP_SUB_Type; + +/** + * @brief GLB DSP codec sub type definition + */ +typedef enum { + GLB_DSP_CODEC_SUB_MJPEG = 1, /*!< mjpeg */ + GLB_DSP_CODEC_SUB_CNN = 2, /*!< BLAI */ + GLB_DSP_CODEC_SUB_VRAM = 16, /*!< vram control logic(SRAM content would not be reset) */ +} GLB_DSP_CODEC_SUB_Type; + +/** + * @brief GLB DSP image sensor type definition + */ +typedef enum { + GLB_DSP_IMAGE_SENSOR_RG_IS = 1, /*!< Image sensor */ +} GLB_DSP_IMAGE_SENSOR_Type; + +/** + * @brief GLB LDO15CIS level type definition + */ +typedef enum { + GLB_LDO15CIS_LEVEL_1P00V = 0, /*!< GLB LDO15CIS voltage 1.00V */ + GLB_LDO15CIS_LEVEL_1P05V = 1, /*!< GLB LDO15CIS voltage 1.05V */ + GLB_LDO15CIS_LEVEL_1P10V = 2, /*!< GLB LDO15CIS voltage 1.10V */ + GLB_LDO15CIS_LEVEL_1P15V = 3, /*!< GLB LDO15CIS voltage 1.15V */ + GLB_LDO15CIS_LEVEL_1P20V = 4, /*!< GLB LDO15CIS voltage 1.20V */ + GLB_LDO15CIS_LEVEL_1P30V = 5, /*!< GLB LDO15CIS voltage 1.30V */ + GLB_LDO15CIS_LEVEL_1P40V = 6, /*!< GLB LDO15CIS voltage 1.40V */ + GLB_LDO15CIS_LEVEL_1P45V = 7, /*!< GLB LDO15CIS voltage 1.45V */ + GLB_LDO15CIS_LEVEL_1P50V = 8, /*!< GLB LDO15CIS voltage 1.50V */ + GLB_LDO15CIS_LEVEL_1P55V = 9, /*!< GLB LDO15CIS voltage 1.55V */ + GLB_LDO15CIS_LEVEL_1P60V = 10, /*!< GLB LDO15CIS voltage 1.60V */ + GLB_LDO15CIS_LEVEL_1P65V = 11, /*!< GLB LDO15CIS voltage 1.65V */ + GLB_LDO15CIS_LEVEL_1P70V = 12, /*!< GLB LDO15CIS voltage 1.70V */ + GLB_LDO15CIS_LEVEL_1P75V = 13, /*!< GLB LDO15CIS voltage 1.75V */ + GLB_LDO15CIS_LEVEL_1P80V = 14, /*!< GLB LDO15CIS voltage 1.80V */ + GLB_LDO15CIS_LEVEL_1P85V = 15, /*!< GLB LDO15CIS voltage 1.85V */ +} GLB_LDO15CIS_LEVEL_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_CORE_ID_TYPE + * @{ + */ +#define IS_GLB_CORE_ID_TYPE(type) (((type) == GLB_CORE_ID_M0) || \ + ((type) == GLB_CORE_ID_D0) || \ + ((type) == GLB_CORE_ID_LP) || \ + ((type) == GLB_CORE_ID_MAX) || \ + ((type) == GLB_CORE_ID_INVALID)) + +/** @defgroup CCI_ID_TYPE + * @{ + */ +#define IS_CCI_ID_TYPE(type) (((type) == CCI0_ID) || \ + ((type) == CCI_ID_MAX)) + +/** @defgroup GLB_DSP_ALL_INT_TYPE + * @{ + */ +#define IS_GLB_DSP_ALL_INT_TYPE(type) (((type) == GLB_DSP_ALL_INT_BUS_DEC_ERR_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV1_INT) || \ + ((type) == GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_RSV3) || \ + ((type) == GLB_DSP_ALL_INT_UART0_INT) || \ + ((type) == GLB_DSP_ALL_INT_I2C0_INT) || \ + ((type) == GLB_DSP_ALL_INT_I2C1_INT) || \ + ((type) == GLB_DSP_ALL_INT_SPI_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV4_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV5_INT) || \ + ((type) == GLB_DSP_ALL_INT_SEOF1_INT) || \ + ((type) == GLB_DSP_ALL_INT_SEOF2_INT) || \ + ((type) == GLB_DSP_ALL_INT_SEOF3_INT) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_0) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_1) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_2) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_INT_3) || \ + ((type) == GLB_DSP_ALL_INT_H264_BS_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_H264_FRAME_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_H264_SEQ_DONE_INT) || \ + ((type) == GLB_DSP_ALL_INT_MJPEG_INT) || \ + ((type) == GLB_DSP_ALL_INT_H264_S_BS_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_H264_S_FRAME_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_H264_S_SEQ_DONE_INT) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_0) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_1) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_2) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_3) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_4) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_5) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_6) || \ + ((type) == GLB_DSP_ALL_INT_DMA_INTR_7) || \ + ((type) == GLB_DSP_ALL_INT_RSV32) || \ + ((type) == GLB_DSP_ALL_INT_RSV33) || \ + ((type) == GLB_DSP_ALL_INT_RSV34) || \ + ((type) == GLB_DSP_ALL_INT_RSV35) || \ + ((type) == GLB_DSP_ALL_INT_RSV36) || \ + ((type) == GLB_DSP_ALL_INT_MIPI_CSI_INT) || \ + ((type) == GLB_DSP_ALL_INT_IPC2_AP2NP_IRQ) || \ + ((type) == GLB_DSP_ALL_INT_RSV39) || \ + ((type) == GLB_DSP_ALL_INT_MJDEC_INT) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_4) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_5) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_6) || \ + ((type) == GLB_DSP_ALL_INT_DVP2BUS_IN_7) || \ + ((type) == GLB_DSP_ALL_INT_DMA2D_INT_0) || \ + ((type) == GLB_DSP_ALL_INT_DMA2D_INT_1) || \ + ((type) == GLB_DSP_ALL_INT_DP_SOEF0_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV48) || \ + ((type) == GLB_DSP_ALL_INT_RSV49) || \ + ((type) == GLB_DSP_ALL_INT_RSV50) || \ + ((type) == GLB_DSP_ALL_INT_RSV51) || \ + ((type) == GLB_DSP_ALL_INT_OSDDP_INT) || \ + ((type) == GLB_DSP_ALL_INT_DBI_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV6_INT) || \ + ((type) == GLB_DSP_ALL_INT_OSDA_INT) || \ + ((type) == GLB_DSP_ALL_INT_OSDB_INT) || \ + ((type) == GLB_DSP_ALL_INT_OSD_PB_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV7_INT) || \ + ((type) == GLB_DSP_ALL_INT_MIPI_DSI_INT) || \ + ((type) == GLB_DSP_ALL_INT_RSV8_INT) || \ + ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ2) || \ + ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ3) || \ + ((type) == GLB_DSP_ALL_INT_MM_WDT_IRQ)) + +/** @defgroup GLB_MCU_ALL_INT_TYPE + * @{ + */ +#define IS_GLB_MCU_ALL_INT_TYPE(type) (((type) == GLB_MCU_ALL_INT_BMX_ERR_INT) || \ + ((type) == GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT) || \ + ((type) == GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_AUDIO_INT) || \ + ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_0) || \ + ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_1) || \ + ((type) == GLB_MCU_ALL_INT_LZ4_INT) || \ + ((type) == GLB_MCU_ALL_INT_RSV8) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT) || \ + ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT) || \ + ((type) == GLB_MCU_ALL_INT_DMA_INTR_ALL) || \ + ((type) == GLB_MCU_ALL_INT_DMA2_INTR_ALL) || \ + ((type) == GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1) || \ + ((type) == GLB_MCU_ALL_INT_MM_IRQ_ALL) || \ + ((type) == GLB_MCU_ALL_INT_IRTX_INT) || \ + ((type) == GLB_MCU_ALL_INT_IRRX_INT) || \ + ((type) == GLB_MCU_ALL_INT_USB_INT) || \ + ((type) == GLB_MCU_ALL_INT_AUPDM_INT) || \ + ((type) == GLB_MCU_ALL_INT_SF_CTRL_ID0_INT) || \ + ((type) == GLB_MCU_ALL_INT_EMAC_INT) || \ + ((type) == GLB_MCU_ALL_INT_GPADC_DMA_INT) || \ + ((type) == GLB_MCU_ALL_INT_EFUSE_INT) || \ + ((type) == GLB_MCU_ALL_INT_SPI_0_INT) || \ + ((type) == GLB_MCU_ALL_INT_UART_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_UART1_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_UART2_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_GPIO_DMA_INT) || \ + ((type) == GLB_MCU_ALL_INT_I2C_0_INT) || \ + ((type) == GLB_MCU_ALL_INT_PWM_INT) || \ + ((type) == GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_TIMER0_2_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_TIMER0_3_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_WDT0_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_I2C_1_INT) || \ + ((type) == GLB_MCU_ALL_INT_I2S0_INT) || \ + ((type) == GLB_MCU_ALL_INT_RSV41) || \ + ((type) == GLB_MCU_ALL_INT_RSV42) || \ + ((type) == GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_GPIO_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_DM_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_BT_IRQ) || \ + ((type) == GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT) || \ + ((type) == GLB_MCU_ALL_INT_M154_INT) || \ + ((type) == GLB_MCU_ALL_INT_M154_AES_INT) || \ + ((type) == GLB_MCU_ALL_INT_PDS_INT) || \ + ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_0) || \ + ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_1) || \ + ((type) == GLB_MCU_ALL_INT_BOR_OUT) || \ + ((type) == GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N) || \ + ((type) == GLB_MCU_ALL_INT_BZ_PHY_INT) || \ + ((type) == GLB_MCU_ALL_INT_BLE_INT) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_GEN) || \ + ((type) == GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER) || \ + ((type) == GLB_MCU_ALL_INT_WIFI_IPC)) + +/** @defgroup GLB_LP_ALL_INT_TYPE + * @{ + */ +#define IS_GLB_LP_ALL_INT_TYPE(type) (((type) == GLB_LP_ALL_INT_BMX_ERR_INT) || \ + ((type) == GLB_LP_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT) || \ + ((type) == GLB_LP_ALL_INT_IPC0_NP2AP_IRQ) || \ + ((type) == GLB_LP_ALL_INT_IPC0_AP2NP_IRQ) || \ + ((type) == GLB_LP_ALL_INT_AUDIO_INT) || \ + ((type) == GLB_LP_ALL_INT_RF_TOP_INT_0) || \ + ((type) == GLB_LP_ALL_INT_RF_TOP_INT_1) || \ + ((type) == GLB_LP_ALL_INT_LZ4_INT) || \ + ((type) == GLB_LP_ALL_INT_RSV8) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_GMAC_INT) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_CDET_INT) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_PKA_INT) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_TRNG_INT) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_AES_INT) || \ + ((type) == GLB_LP_ALL_INT_SEC_ENG_ID0_SHA_INT) || \ + ((type) == GLB_LP_ALL_INT_DMA_INTR_ALL) || \ + ((type) == GLB_LP_ALL_INT_DMA2_INTR_ALL) || \ + ((type) == GLB_LP_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1) || \ + ((type) == GLB_LP_ALL_INT_MM_IRQ_ALL) || \ + ((type) == GLB_LP_ALL_INT_IRTX_INT) || \ + ((type) == GLB_LP_ALL_INT_IRRX_INT) || \ + ((type) == GLB_LP_ALL_INT_USB_INT) || \ + ((type) == GLB_LP_ALL_INT_AUPDM_INT) || \ + ((type) == GLB_LP_ALL_INT_SF_CTRL_ID0_INT) || \ + ((type) == GLB_LP_ALL_INT_EMAC_INT) || \ + ((type) == GLB_LP_ALL_INT_GPADC_DMA_INT) || \ + ((type) == GLB_LP_ALL_INT_EFUSE_INT) || \ + ((type) == GLB_LP_ALL_INT_SPI_0_INT) || \ + ((type) == GLB_LP_ALL_INT_UART_IRQ) || \ + ((type) == GLB_LP_ALL_INT_UART1_IRQ) || \ + ((type) == GLB_LP_ALL_INT_UART2_IRQ) || \ + ((type) == GLB_LP_ALL_INT_GPIO_DMA_INT) || \ + ((type) == GLB_LP_ALL_INT_I2C_0_INT) || \ + ((type) == GLB_LP_ALL_INT_PWM_INT) || \ + ((type) == GLB_LP_ALL_INT_IPC1_NP2AP_IRQ) || \ + ((type) == GLB_LP_ALL_INT_IPC1_AP2NP_IRQ) || \ + ((type) == GLB_LP_ALL_INT_TIMER0_2_IRQ) || \ + ((type) == GLB_LP_ALL_INT_TIMER0_3_IRQ) || \ + ((type) == GLB_LP_ALL_INT_WDT0_IRQ) || \ + ((type) == GLB_LP_ALL_INT_I2C_1_INT) || \ + ((type) == GLB_LP_ALL_INT_I2S0_INT) || \ + ((type) == GLB_LP_ALL_INT_RSV41) || \ + ((type) == GLB_LP_ALL_INT_RSV42) || \ + ((type) == GLB_LP_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ) || \ + ((type) == GLB_LP_ALL_INT_GPIO_IRQ) || \ + ((type) == GLB_LP_ALL_INT_DM_IRQ) || \ + ((type) == GLB_LP_ALL_INT_BT_IRQ) || \ + ((type) == GLB_LP_ALL_INT_M154_REQ_ENH_ACK_INT) || \ + ((type) == GLB_LP_ALL_INT_M154_INT) || \ + ((type) == GLB_LP_ALL_INT_M154_AES_INT) || \ + ((type) == GLB_LP_ALL_INT_PDS_INT) || \ + ((type) == GLB_LP_ALL_INT_HBN_IRQ_OUT_0) || \ + ((type) == GLB_LP_ALL_INT_HBN_IRQ_OUT_1) || \ + ((type) == GLB_LP_ALL_INT_BOR_OUT) || \ + ((type) == GLB_LP_ALL_INT_WIFI_TO_CPU_IRQ_N) || \ + ((type) == GLB_LP_ALL_INT_BZ_PHY_INT) || \ + ((type) == GLB_LP_ALL_INT_BLE_INT) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_TX_RX_TIMER) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_TX_RX_MISC) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_RX_TRIGGER) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_TX_TRIGGER) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_GEN) || \ + ((type) == GLB_LP_ALL_INT_MAC_INT_PROT_TRIGGER) || \ + ((type) == GLB_LP_ALL_INT_WIFI_IPC)) + +/** @defgroup GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_320M) || \ + ((type) == GLB_DSP_MUXPLL_SEL_AUPLL_DIV1)) + +/** @defgroup GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_240M) || \ + ((type) == GLB_DSP_MUXPLL_SEL_AUPLL_DIV2)) + +/** @defgroup GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(type) (((type) == GLB_DSP_MUXPLL_SEL_WIFIPLL_160M) || \ + ((type) == GLB_DSP_MUXPLL_SEL_CPUPLL_160M)) + +/** @defgroup GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_160M) || \ + ((type) == GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_160M) || \ + ((type) == GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2) || \ + ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5)) + +/** @defgroup GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_80M) || \ + ((type) == GLB_MCU_MUXPLL_SEL_TOP_CPUPLL_80M) || \ + ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV5) || \ + ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV6)) + +/** @defgroup GLB_PLL_CGEN_TYPE + * @{ + */ +#define IS_GLB_PLL_CGEN_TYPE(type) (((type) == GLB_PLL_CGEN_MM_WIFIPLL_160M) || \ + ((type) == GLB_PLL_CGEN_MM_WIFIPLL_240M) || \ + ((type) == GLB_PLL_CGEN_MM_WIFIPLL_320M) || \ + ((type) == GLB_PLL_CGEN_MM_AUPLL_DIV1) || \ + ((type) == GLB_PLL_CGEN_MM_AUPLL_DIV2) || \ + ((type) == GLB_PLL_CGEN_EMI_CPUPLL_400M) || \ + ((type) == GLB_PLL_CGEN_EMI_CPUPLL_200M) || \ + ((type) == GLB_PLL_CGEN_EMI_WIFIPLL_320M) || \ + ((type) == GLB_PLL_CGEN_EMI_AUPLL_DIV1) || \ + ((type) == GLB_PLL_CGEN_TOP_CPUPLL_80M) || \ + ((type) == GLB_PLL_CGEN_TOP_CPUPLL_100M) || \ + ((type) == GLB_PLL_CGEN_TOP_CPUPLL_160M) || \ + ((type) == GLB_PLL_CGEN_TOP_CPUPLL_400M) || \ + ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_240M) || \ + ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_320M) || \ + ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV2) || \ + ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV1)) + +/** @defgroup GLB_MCU_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_MCU_SYS_CLK_TYPE(type) (((type) == GLB_MCU_SYS_CLK_RC32M) || \ + ((type) == GLB_MCU_SYS_CLK_XTAL) || \ + ((type) == GLB_MCU_SYS_CLK_CPUPLL_400M) || \ + ((type) == GLB_MCU_SYS_CLK_WIFIPLL_240M) || \ + ((type) == GLB_MCU_SYS_CLK_WIFIPLL_320M)) + +/** @defgroup GLB_DSP_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_SYS_CLK_TYPE(type) (((type) == GLB_DSP_SYS_CLK_RC32M) || \ + ((type) == GLB_DSP_SYS_CLK_XTAL) || \ + ((type) == GLB_DSP_SYS_CLK_MM_WIFIPLL_240M) || \ + ((type) == GLB_DSP_SYS_CLK_MM_WIFIPLL_320M) || \ + ((type) == GLB_DSP_SYS_CLK_CPUPLL_400M)) + +/** @defgroup GLB_DSP_SYS_PBCLK_TYPE + * @{ + */ +#define IS_GLB_DSP_SYS_PBCLK_TYPE(type) (((type) == GLB_DSP_SYS_PBCLK_RC32M) || \ + ((type) == GLB_DSP_SYS_PBCLK_XTAL) || \ + ((type) == GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M) || \ + ((type) == GLB_DSP_SYS_PBCLK_CPUPLL_160M) || \ + ((type) == GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M)) + +/** @defgroup GLB_PLL_REF_CLK_TYPE + * @{ + */ +#define IS_GLB_PLL_REF_CLK_TYPE(type) (((type) == GLB_PLL_REFCLK_XTAL) || \ + ((type) == GLB_PLL_REFCLK_RC32M)) + +/** @defgroup GLB_WIFIPLL_REF_CLK_Type + * @{ + */ +#define IS_GLB_WIFIPLL_REF_CLK_TYPE(type) (((type) == GLB_WIFIPLL_REF_XTAL_SOC_CLK) || \ + ((type) == GLB_WIFIPLL_REF_XTAL_CLK) || \ + ((type) == GLB_WIFIPLL_REF_XTAL_LO_CLK) || \ + ((type) == GLB_WIFIPLL_REF_RC32M_CLK)) + +/** @defgroup GLB_AUPLL_REF_CLK_Type + * @{ + */ +#define IS_GLB_AUPLL_REF_CLK_TYPE(type) (((type) == GLB_AUPLL_REF_XTAL_SOC_CLK) || \ + ((type) == GLB_AUPLL_REF_RC32M_CLK)) + +/** @defgroup GLB_CPUPLL_REF_CLK_Type + * @{ + */ +#define IS_GLB_CPUPLL_REF_CLK_TYPE(type) (((type) == GLB_CPUPLL_REF_XTAL_SOC_CLK) || \ + ((type) == GLB_CPUPLL_REF_RC32M_CLK)) + +/** @defgroup GLB_MIPIPLL_REF_CLK_Type + * @{ + */ +#define IS_GLB_MIPIPLL_REF_CLK_TYPE(type) (((type) == GLB_MIPIPLL_REF_XTAL_SOC_CLK) || \ + ((type) == GLB_MIPIPLL_REF_RC32M_CLK)) + +/** @defgroup GLB_UHSPLL_REF_CLK_Type + * @{ + */ +#define IS_GLB_UHSPLL_REF_CLK_TYPE(type) (((type) == GLB_UHSPLL_REF_XTAL_SOC_CLK) || \ + ((type) == GLB_UHSPLL_REF_RC32M_CLK)) + +/** @defgroup GLB_CAM_CLK_TYPE + * @{ + */ +#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \ + ((type) == GLB_CAM_CLK_WIFIPLL_96M) || \ + ((type) == GLB_CAM_CLK_CPUPLL_100M)) + +/** @defgroup GLB_SDH_CLK_TYPE + * @{ + */ +#define IS_GLB_SDH_CLK_TYPE(type) (((type) == GLB_SDH_CLK_WIFIPLL_96M) || \ + ((type) == GLB_SDH_CLK_CPUPLL_100M)) + +/** @defgroup GLB_GLB_UART_SIG_SWAP_SET_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_SWAP_GRP_TYPE(type) (((type) == GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11) || \ + ((type) == GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23) || \ + ((type) == GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35) || \ + ((type) == GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45)) + +/** @defgroup GLB_I2S_OUT_REF_CLK_TYPE + * @{ + */ +#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \ + ((type) == GLB_I2S_OUT_REF_CLK_SRC)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA0_CLK_CH0) || \ + ((type) == GLB_DMA0_CLK_CH1) || \ + ((type) == GLB_DMA0_CLK_CH2) || \ + ((type) == GLB_DMA0_CLK_CH3) || \ + ((type) == GLB_DMA0_CLK_CH4) || \ + ((type) == GLB_DMA0_CLK_CH5) || \ + ((type) == GLB_DMA0_CLK_CH6) || \ + ((type) == GLB_DMA0_CLK_CH7) || \ + ((type) == GLB_DMA1_CLK_CH0) || \ + ((type) == GLB_DMA1_CLK_CH1) || \ + ((type) == GLB_DMA1_CLK_CH2) || \ + ((type) == GLB_DMA1_CLK_CH3)) + +/** @defgroup GLB_PERI_DMA_TYPE + * @{ + */ +#define IS_GLB_PERI_DMA_TYPE(type) (((type) == GLB_PERI_DMA_UART0_RX) || \ + ((type) == GLB_PERI_DMA_UART0_TX) || \ + ((type) == GLB_PERI_DMA_UART1_RX) || \ + ((type) == GLB_PERI_DMA_UART1_TX) || \ + ((type) == GLB_PERI_DMA_UART2_RX) || \ + ((type) == GLB_PERI_DMA_UART2_TX) || \ + ((type) == GLB_PERI_DMA_I2C_0_RX) || \ + ((type) == GLB_PERI_DMA_I2C_0_TX) || \ + ((type) == GLB_PERI_DMA_IRTX_TX) || \ + ((type) == GLB_PERI_DMA_GPIO_TX) || \ + ((type) == GLB_PERI_DMA_SPI_RX) || \ + ((type) == GLB_PERI_DMA_SPI_TX) || \ + ((type) == GLB_PERI_DMA_AUDIO_RX) || \ + ((type) == GLB_PERI_DMA_AUDIO_TX) || \ + ((type) == GLB_PERI_DMA_I2C_1_RX) || \ + ((type) == GLB_PERI_DMA_I2C_1_TX) || \ + ((type) == GLB_PERI_DMA_I2S_0_RX) || \ + ((type) == GLB_PERI_DMA_I2S_0_TX) || \ + ((type) == GLB_PERI_DMA_PDM_RX) || \ + ((type) == GLB_PERI_DMA_PADC) || \ + ((type) == GLB_PERI_DMA_GAUGE) || \ + ((type) == GLB_PERI_DMA_GPADC) || \ + ((type) == GLB_PERI_DMA_GPDAC_TX)) + +/** @defgroup GLB_PERI_DMA_CN_SEL_TYPE + * @{ + */ +#define IS_GLB_PERI_DMA_CN_SEL_TYPE(type) (((type) == GLB_PERI_DMA_CN_SEL_DMA0) || \ + ((type) == GLB_PERI_DMA_CN_SEL_DMA1)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M_WIFIPLL) || \ + ((type) == GLB_SFLASH_CLK_XTAL) || \ + ((type) == GLB_SFLASH_CLK_100M_CPUPLL) || \ + ((type) == GLB_SFLASH_CLK_80M_MUXPLL) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_96M_WIFIPLL)) + +/** @defgroup GLB_I2C_CLK_TYPE + * @{ + */ +#define IS_GLB_I2C_CLK_TYPE(type) (((type) == GLB_I2C_CLK_BCLK) || \ + ((type) == GLB_I2C_CLK_XCLK)) + +/** @defgroup GLB_SPI_CLK_TYPE + * @{ + */ +#define IS_GLB_SPI_CLK_TYPE(type) (((type) == GLB_SPI_CLK_PLL160M) || \ + ((type) == GLB_SPI_CLK_XCLK)) + +/** @defgroup GLB_PWM1_IO_SEL_TYPE + * @{ + */ +#define IS_GLB_PWM1_IO_SEL_TYPE(type) (((type) == GLB_PWM1_IO_SINGLE_END) || \ + ((type) == GLB_PWM1_IO_DIFF_END)) + +/** @defgroup GLB_PWM2_IO_SEL_TYPE + * @{ + */ +#define IS_GLB_PWM2_IO_SEL_TYPE(type) (((type) == GLB_PWM2_IO_SINGLE_END) || \ + ((type) == GLB_PWM2_IO_SINGLE_END_BLDC)) + +/** @defgroup GLB_PDM_IO_SEL_TYPE + * @{ + */ +#define IS_GLB_PDM_IO_SEL_TYPE(type) (((type) == GLB_PDM_IO_SEL_AUDIO_TOP) || \ + ((type) == GLB_PDM_IO_SEL_AUPDM_TOP)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_AHB_SW_TYPE + * @{ + */ +#define IS_GLB_AHB_MCU_SW_TYPE(type) (((type) == GLB_AHB_MCU_SW_RSV0) || \ + ((type) == GLB_AHB_MCU_SW_RSV1) || \ + ((type) == GLB_AHB_MCU_SW_WIFI) || \ + ((type) == GLB_AHB_MCU_SW_BTDM) || \ + ((type) == GLB_AHB_MCU_SW_ZIGBEE) || \ + ((type) == GLB_AHB_MCU_SW_BLE2) || \ + ((type) == GLB_AHB_MCU_SW_ZIGBEE2) || \ + ((type) == GLB_AHB_MCU_SW_EMI_MISC) || \ + ((type) == GLB_AHB_MCU_SW_PSRAM0_CTRL) || \ + ((type) == GLB_AHB_MCU_SW_PSRAM1_CTRL) || \ + ((type) == GLB_AHB_MCU_SW_USB) || \ + ((type) == GLB_AHB_MCU_SW_MIX2) || \ + ((type) == GLB_AHB_MCU_SW_AUDIO) || \ + ((type) == GLB_AHB_MCU_SW_SDH) || \ + ((type) == GLB_AHB_MCU_SW_EMAC) || \ + ((type) == GLB_AHB_MCU_SW_DMA2) || \ + ((type) == GLB_AHB_MCU_SW_GLB) || \ + ((type) == GLB_AHB_MCU_SW_MIX) || \ + ((type) == GLB_AHB_MCU_SW_GPIP) || \ + ((type) == GLB_AHB_MCU_SW_SEC_DBG) || \ + ((type) == GLB_AHB_MCU_SW_SEC_ENG) || \ + ((type) == GLB_AHB_MCU_SW_TZ1) || \ + ((type) == GLB_AHB_MCU_SW_TZ2) || \ + ((type) == GLB_AHB_MCU_SW_EFUSE) || \ + ((type) == GLB_AHB_MCU_SW_CCI) || \ + ((type) == GLB_AHB_MCU_SW_L1C) || \ + ((type) == GLB_AHB_MCU_SW_RSV42) || \ + ((type) == GLB_AHB_MCU_SW_SF) || \ + ((type) == GLB_AHB_MCU_SW_DMA) || \ + ((type) == GLB_AHB_MCU_SW_SDU) || \ + ((type) == GLB_AHB_MCU_SW_PDS) || \ + ((type) == GLB_AHB_MCU_SW_RSV47) || \ + ((type) == GLB_AHB_MCU_SW_UART0) || \ + ((type) == GLB_AHB_MCU_SW_UART1) || \ + ((type) == GLB_AHB_MCU_SW_SPI) || \ + ((type) == GLB_AHB_MCU_SW_I2C) || \ + ((type) == GLB_AHB_MCU_SW_PWM) || \ + ((type) == GLB_AHB_MCU_SW_TIMER) || \ + ((type) == GLB_AHB_MCU_SW_IR_REMOTE) || \ + ((type) == GLB_AHB_MCU_SW_CHECKSUM) || \ + ((type) == GLB_AHB_MCU_SW_QDEC) || \ + ((type) == GLB_AHB_MCU_SW_KYS) || \ + ((type) == GLB_AHB_MCU_SW_UART2) || \ + ((type) == GLB_AHB_MCU_SW_RSV59) || \ + ((type) == GLB_AHB_MCU_SW_RSV60) || \ + ((type) == GLB_AHB_MCU_SW_RSV61) || \ + ((type) == GLB_AHB_MCU_SW_RSV62) || \ + ((type) == GLB_AHB_MCU_SW_RSV63) || \ + ((type) == GLB_AHB_MCU_SW_PWRON_RST) || \ + ((type) == GLB_AHB_MCU_SW_CPU_RESET) || \ + ((type) == GLB_AHB_MCU_SW_SYS_RESET) || \ + ((type) == GLB_AHB_MCU_SW_PICO_RESET) || \ + ((type) == GLB_AHB_MCU_SW_CPU2_RESET) || \ + ((type) == GLB_AHB_MCU_SW_CHIP_RESET) || \ + ((type) == GLB_AHB_MCU_SW_WL_WDT_RESET_MM_EN) || \ + ((type) == GLB_AHB_MCU_SW_MMWDT2WL_RST_MSK)) + +/** @defgroup GLB_AHB_DSP_SW_TYPE + * @{ + */ +#define IS_GLB_AHB_DSP_SW_TYPE(type) (((type) == GLB_AHB_DSP_SW_REG_CTRL_SYS_RESET) || \ + ((type) == GLB_AHB_DSP_SW_REG_CTRL_PWRON_RST) || \ + ((type) == GLB_AHB_DSP_SW_REG_CTRL_MMCPU0_RESET) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_MM_MISC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DMA) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_UART0) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_I2C0) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_I2C1) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_IPC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DMA2D) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_SPI) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_TIMER) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_I2S0) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_I2S1) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_PDM0) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_PDM1) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_PUHS) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MISC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MAIN) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_SUB_TSRC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DP_TSRC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_NR3D_CTRL) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSA) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSB) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSD) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_MIPI) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_SUB_REG) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSE) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSF) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSG) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSH) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_CODEC_MISC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_MJPEG) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_H264) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_MJPEG_DEC) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_CNN) || \ + ((type) == GLB_AHB_DSP_SW_SWRST_VRAM) || \ + ((type) == GLB_AHB_DSP_SW_RG_IS_RST_N)) + +/** @defgroup GLB DISRST_TYPE + * @{ + */ +#define IS_GLB_DISRST_TYPE(type) (((type) == GLB_DISRST_GPIP) || \ + ((type) == GLB_DISRST_SEC_ENG) || \ + ((type) == GLB_DISRST_CCI) || \ + ((type) == GLB_DISRST_SF) || \ + ((type) == GLB_DISRST_UART0) || \ + ((type) == GLB_DISRST_UART1) || \ + ((type) == GLB_DISRST_SPI) || \ + ((type) == GLB_DISRST_I2C0) || \ + ((type) == GLB_DISRST_PWM) || \ + ((type) == GLB_DISRST_TIMER) || \ + ((type) == GLB_DISRST_IR_REMOTE) || \ + ((type) == GLB_DISRST_CHECKSUM) || \ + ((type) == GLB_DISRST_IPC) || \ + ((type) == GLB_DISRST_I2C1) || \ + ((type) == GLB_DISRST_UART2)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_MCU_BCLK) || \ + ((type) == GLB_PKA_CLK_MCU_MUXPLL_160M)) + +/** @defgroup GLB_MCU_SW_SYSTEM_TYPE + * @{ + */ +#define IS_GLB_MCU_SW_SYSTEM_TYPE(type) (((type) == GLB_MCU_SW_SYSTEM_CTRL_MCU) || \ + ((type) == GLB_MCU_SW_SYSTEM_CTRL_LP)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_FIX)) + +/** @defgroup BMX_LATCH_TYPE + * @{ + */ +#define IS_BMX_LATCH_TYPE(type) (((type) == BMX_LATCH_FIRST_ERROR) || \ + ((type) == BMX_LATCH_LAST_ERROR)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_ETH_REF_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \ + ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_WRAM160KB_EM0KB) || \ + ((type) == GLB_WRAM144KB_EM16KB) || \ + ((type) == GLB_WRAM128KB_EM32KB) || \ + ((type) == GLB_WRAM112KB_EM48KB) || \ + ((type) == GLB_WRAM96KB_EM64KB)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUPLL) || \ + ((type) == GLB_ADC_CLK_XCLK)) + +/** @defgroup GLB_DAC_CLK_TYPE + * @{ + */ +#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \ + ((type) == GLB_DAC_CLK_XCLK)) + +/** @defgroup GLB_CHIP_CLK_INOUT_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_INOUT_TYPE(type) (((type) == GLB_CHIP_CLK_INOUT_INPUT) || \ + ((type) == GLB_CHIP_CLK_INOUT_OUTPUT)) + +/** @defgroup GLB_CHIP_CLK_OUT_0_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_0_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_0_CAM_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_0_I2S_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_0_CLK_AUDIO_ADC) || \ + ((type) == GLB_CHIP_CLK_OUT_0_CLK_AUDIO_DAC)) + +/** @defgroup GLB_CHIP_CLK_OUT_1_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_1_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_1_CAM_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_1_I2S_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_1_CLK_AUDIO_ADC) || \ + ((type) == GLB_CHIP_CLK_OUT_1_CLK_AUDIO_DAC)) + +/** @defgroup GLB_CHIP_CLK_OUT_2_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_2_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_2_CAM_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_2_I2S_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_2_PLL_32M_CLK)) + +/** @defgroup GLB_CHIP_CLK_OUT_3_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_3_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_3_CAM_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_3_I2S_REF_CLK) || \ + ((type) == GLB_CHIP_CLK_OUT_3_NONE) || \ + ((type) == GLB_CHIP_CLK_OUT_3_PLL_48M_CLK)) + +/** @defgroup GLB_CSI_DSI_CLK_SEL_TYPE + * @{ + */ +#define IS_GLB_CSI_DSI_CLK_SEL_TYPE(type) (((type) == GLB_CSI_DSI_CLK_SEL_XTAL_CLK) || \ + ((type) == GLB_CSI_DSI_CLK_SEL_CPUPLL_DIV10)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_WIFIPLL_32M) || \ + ((type) == GLB_DIG_CLK_XCLK) || \ + ((type) == GLB_DIG_CLK_AUPLL)) + +/** @defgroup GLB_512K_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \ + ((type) == GLB_512K_CLK_OUT_256K) || \ + ((type) == GLB_512K_CLK_OUT_128K)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART2_IO_SEL_TYPE + * @{ + */ +#define IS_GLB_UART2_IO_SEL_TYPE(type) (((type) == GLB_UART2_IO_SEL_UART2) || \ + ((type) == GLB_UART2_IO_SEL_ISO11898)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3) || \ + ((type) == GLB_UART_SIG_4) || \ + ((type) == GLB_UART_SIG_5) || \ + ((type) == GLB_UART_SIG_6) || \ + ((type) == GLB_UART_SIG_7) || \ + ((type) == GLB_UART_SIG_8) || \ + ((type) == GLB_UART_SIG_9) || \ + ((type) == GLB_UART_SIG_10) || \ + ((type) == GLB_UART_SIG_11)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART2_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART2_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART2_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART2_RXD)) + +/** @defgroup GLB_XTAL_TYPE + * @{ + */ +#define IS_GLB_XTAL_TYPE(type) (((type) == GLB_XTAL_NONE) || \ + ((type) == GLB_XTAL_24M) || \ + ((type) == GLB_XTAL_32M) || \ + ((type) == GLB_XTAL_38P4M) || \ + ((type) == GLB_XTAL_40M) || \ + ((type) == GLB_XTAL_26M) || \ + ((type) == GLB_XTAL_RC32M) || \ + ((type) == GLB_XTAL_MAX)) + +/** @defgroup GLB_PLL_TYPE + * @{ + */ +#define IS_GLB_PLL_TYPE(type) (((type) == GLB_PLL_NONE) || \ + ((type) == GLB_PLL_WIFIPLL) || \ + ((type) == GLB_PLL_AUPLL) || \ + ((type) == GLB_PLL_CPUPLL) || \ + ((type) == GLB_PLL_MIPIPLL) || \ + ((type) == GLB_PLL_UHSPLL)) + +/** @defgroup GLB_WAC_PLL_TYPE + * @{ + */ +#define IS_GLB_WAC_PLL_TYPE(type) (((type) == GLB_WAC_PLL_WIFIPLL) || \ + ((type) == GLB_WAC_PLL_AUPLL) || \ + ((type) == GLB_WAC_PLL_CPUPLL)) + +/** @defgroup GLB_MU_PLL_TYPE + * @{ + */ +#define IS_GLB_MU_PLL_TYPE(type) (((type) == GLB_MU_PLL_MIPIPLL) || \ + ((type) == GLB_MU_PLL_UHSPLL)) + +/** @defgroup GLB_DISP_CLK_TYPE + * @{ + */ +#define IS_GLB_DISP_CLK_TYPE(type) (((type) == GLB_DISP_CLK_MIPIPLL_1500M)) + +/** @defgroup GLB_PSRAM_PLL_TYPE + * @{ + */ +#define IS_GLB_PSRAM_PLL_TYPE(type) (((type) == GLB_PSRAM_EMI_CPUPLL_400M) || \ + ((type) == GLB_PSRAM_EMI_WIFIPLL_320M) || \ + ((type) == GLB_PSRAM_EMI_AUPLL_DIV1)) + +/** @defgroup GLB_DSP_XCLK_TYPE + * @{ + */ +#define IS_GLB_DSP_XCLK_TYPE(type) (((type) == GLB_DSP_XCLK_RC32M) || \ + ((type) == GLB_DSP_XCLK_XTAL)) + +/** @defgroup GLB_DSP_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_ROOT_CLK_TYPE(type) (((type) == GLB_DSP_ROOT_CLK_XCLK) || \ + ((type) == GLB_DSP_ROOT_CLK_PLL)) + +/** @defgroup GLB_DSP_PBROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_PBROOT_CLK_TYPE(type) (((type) == GLB_DSP_PBROOT_CLK_MM_XCLK) || \ + ((type) == GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M) || \ + ((type) == GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M)) + +/** @defgroup GLB_DSP_PLL_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_PLL_CLK_TYPE(type) (((type) == GLB_DSP_PLL_CLK_MUXPLL_240M) || \ + ((type) == GLB_DSP_PLL_CLK_MUXPLL_320M) || \ + ((type) == GLB_DSP_PLL_CLK_CPUPLL_400M)) + +/** @defgroup GLB_DSP_UART_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_UART_CLK_TYPE(type) (((type) == GLB_DSP_UART_CLK_DSP_PBCLK) || \ + ((type) == GLB_DSP_UART_CLK_MUXPLL_160M) || \ + ((type) == GLB_DSP_UART_CLK_DSP_XCLK)) + +/** @defgroup GLB_UART_CLK_TYPE + * @{ + */ +#define IS_GLB_UART_CLK_TYPE(type) (((type) == GLB_UART_CLK_BCLK) || \ + ((type) == GLB_UART_CLK_PLL_160M)) + +/** @defgroup GLB_DSP_CNN_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_CNN_CLK_TYPE(type) (((type) == GLB_DSP_CNN_CLK_160M) || \ + ((type) == GLB_DSP_CNN_CLK_240M) || \ + ((type) == GLB_DSP_CNN_CLK_320M)) + +/** @defgroup GLB_DSP_DP_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_DP_CLK_TYPE(type) (((type) == GLB_DSP_DP_CLK_DISPLAY_PLL) || \ + ((type) == GLB_DSP_DP_CLK_DSP_XCLK)) + +/** @defgroup GLB_DSP_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_CLK_TYPE(type) (((type) == GLB_DSP_CLK_MUXPLL_160M) || \ + ((type) == GLB_DSP_CLK_MUXPLL_240M) || \ + ((type) == GLB_DSP_CLK_CPUPLL_400M) || \ + ((type) == GLB_DSP_CLK_DSP_XCLK)) + +/** @defgroup GLB_DSP_H264_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_H264_CLK_TYPE(type) (((type) == GLB_DSP_H264_DSP_MUXPLL_160M) || \ + ((type) == GLB_DSP_H264_DSP_MUXPLL_240M) || \ + ((type) == GLB_DSP_H264_DSP_MUXPLL_320M)) + +/** @defgroup GLB_DSP_SPI_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_SPI_CLK_TYPE(type) (((type) == GLB_DSP_SPI_CLK_DSP_MUXPLL_160M) || \ + ((type) == GLB_DSP_SPI_CLK_DSP_XCLK)) + +/** @defgroup GLB_DSP_I2C_CLK_TYPE + * @{ + */ +#define IS_GLB_DSP_I2C_CLK_TYPE(type) (((type) == GLB_DSP_I2C_CLK_DSP_PBCLK) || \ + ((type) == GLB_DSP_I2C_CLK_XCLK)) + +/** @defgroup GLB_I2S_DI_REF_CLK_TYPE + * @{ + */ +#define IS_GLB_I2S_DI_REF_CLK_TYPE(type) (((type) == GLB_I2S_DI_SEL_I2S_DI_INPUT) || \ + ((type) == GLB_I2S_DI_SEL_I2S_REF_OUTPUT)) + +/** @defgroup GLB_I2S_DO_REF_CLK_TYPE + * @{ + */ +#define IS_GLB_I2S_DO_REF_CLK_TYPE(type) (((type) == GLB_I2S_DO_SEL_I2S_DO_OUTPT) || \ + ((type) == GLB_I2S_DO_SEL_I2S_REF_OUTPUT)) + +/** @defgroup GLB_EMI_CLK_TYPE + * @{ + */ +#define IS_GLB_EMI_CLK_TYPE(type) (((type) == GLB_EMI_CLK_MCU_PBCLK) || \ + ((type) == GLB_EMI_CLK_CPUPLL_200M_CLK) || \ + ((type) == GLB_EMI_CLK_WIFIPLL_320M_CLK) || \ + ((type) == GLB_EMI_CLK_CPUPLL_400M_CLK)) + +/** @defgroup GLB_DSP_SW_SYSTEM_TYPE + * @{ + */ +#define IS_GLB_DSP_SW_SYSTEM_TYPE(type) (((type) == GLB_DSP_SW_SYSTEM_CTRL_SYS) || \ + ((type) == GLB_DSP_SW_SYSTEM_CTRL_PWRON) || \ + ((type) == GLB_DSP_SW_SYSTEM_CTRL_DSP0) || \ + ((type) == GLB_DSP_SW_SYSTEM_CTRL_DSP1) || \ + ((type) == GLB_DSP_SW_SYSTEM_CTRL_WL2MM)) + +/** @defgroup GLB_DSP_PERIPHERAL_TYPE + * @{ + */ +#define IS_GLB_DSP_PERIPHERAL_TYPE(type) (((type) == GLB_DSP_PERIPHERAL_MM_MISC) || \ + ((type) == GLB_DSP_PERIPHERAL_DMA) || \ + ((type) == GLB_DSP_PERIPHERAL_UART0) || \ + ((type) == GLB_DSP_PERIPHERAL_I2C0) || \ + ((type) == GLB_DSP_PERIPHERAL_IPC) || \ + ((type) == GLB_DSP_PERIPHERAL_SPI) || \ + ((type) == GLB_DSP_PERIPHERAL_TIMER) || \ + ((type) == GLB_DSP_PERIPHERAL_I2S0)) + +/** @defgroup GLB_DSP_SUB_TYPE + * @{ + */ +#define IS_GLB_DSP_SUB_TYPE(type) (((type) == GLB_DSP_SUB_MISC) || \ + ((type) == GLB_DSP_SUB_DVP2BUSA) || \ + ((type) == GLB_DSP_SUB_DVP2BUSB) || \ + ((type) == GLB_DSP_SUB_DVP2BUSC) || \ + ((type) == GLB_DSP_SUB_OSD_DRAW) || \ + ((type) == GLB_DSP_SUB_DP) || \ + ((type) == GLB_DSP_SUB_IMG_PR) || \ + ((type) == GLB_DSP_SUB_SCLRA) || \ + ((type) == GLB_DSP_SUB_SCLRB)) + +/** @defgroup GLB_DSP_CODEC_SUB_TYPE + * @{ + */ +#define IS_GLB_DSP_CODEC_SUB_TYPE(type) (((type) == GLB_DSP_CODEC_SUB_MJPEG) || \ + ((type) == GLB_DSP_CODEC_SUB_CNN) || \ + ((type) == GLB_DSP_CODEC_SUB_VRAM)) + +/** @defgroup GLB_DSP_IMAGE_SENSOR_TYPE + * @{ + */ +#define IS_GLB_DSP_IMAGE_SENSOR_TYPE(type) (((type) == GLB_DSP_IMAGE_SENSOR_RG_IS)) + +/** @defgroup GLB_LDO15CIS_LEVEL_TYPE + * @{ + */ +#define IS_GLB_LDO15CIS_LEVEL_TYPE(type) (((type) == GLB_LDO15CIS_LEVEL_1P00V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P05V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P10V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P15V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P20V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P30V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P40V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P45V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P50V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P55V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P60V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P65V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P70V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P75V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P80V) || \ + ((type) == GLB_LDO15CIS_LEVEL_1P85V)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define UART_SIG_SWAP_NONE (0x00) /* uart_sig[0:11] -> uart_sig[0:11] */ +#define UART_SIG_SWAP_GPIO0_GPIO11 (0x01) /* GPIO0-11 uart_sig[ 0:11] -> uart_sig[ 6:11], uart_sig[ 0: 5] */ +#define UART_SIG_SWAP_GPIO12_GPIO23 (0x02) /* GPIO12-23 uart_sig[12:23] -> uart_sig[18:23], uart_sig[12:17] */ +#define UART_SIG_SWAP_GPIO24_GPIO35 (0x04) /* GPIO24-35 uart_sig[24:35] -> uart_sig[30:35], uart_sig[24:29] */ +#define UART_SIG_SWAP_GPIO36_GPIO47 (0x08) /* GPIO36-47 uart_sig[36:47] -> uart_sig[42:47], uart_sig[36:41] */ + +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +#define GLB_AHB_CLOCK_CPU (0x1ULL<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl808_psram_uhs.h" +#include "bl808_uhs_phy.h" +#include "bl808_common.h" +#include "bl808_glb.h" +#include + +/** @addtogroup BL808_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM_UHS + * @{ + */ + +/** @defgroup PSRAM_UHS_Private_Macros + * @{ + */ +#define PSRAM_UHS_RW_TIMEOUT 0xffffffff +/*@} end of group PSRAM_UHS_Private_Macros */ + +/** @defgroup PSRAM_UHS_Private_Types + * @{ + */ + +/*@} end of group PSRAM_UHS_Private_Types */ + +/** @defgroup PSRAM_UHS_Private_Variables + * @{ + */ + +/*@} end of group PSRAM_UHS_Private_Variables */ + +/** @defgroup PSRAM_UHS_Global_Variables + * @{ + */ + +/*@} end of group PSRAM_UHS_Global_Variables */ + +/** @defgroup PSRAM_UHS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PSRAM_UHS_Private_Fun_Declaration */ + +/** @defgroup PSRAM_UHS_Private_Functions + * @{ + */ + +/*@} end of group PSRAM_UHS_Private_Functions */ + +/** @defgroup PSRAM_UHS_Public_Functions + * @{ + */ +int config_uhs_phy(uint32_t datarate) +{ + uint32_t tmpVal = 0; + + if (datarate > 1866) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F0A1323); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0b030404); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x050e0419); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x0a6a1c1c); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0711070e); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + } else if (datarate > 1600) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F283203); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x091e1818); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0710070d); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 3); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + } else if (datarate > 1066) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x09020303); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040c0313); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x07d11515); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x060f060c); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + } else if (datarate > 800) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x06010202); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0309020d); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x05360e0e); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x050c0509); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + } else if (datarate > 666) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F041020); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0208010a); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03e90b0b); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + } else if (datarate > 400) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F130010); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02080108); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03420909); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + } else { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F020010); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x04000101); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02070106); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x01f50606); + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040a0407); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + } + return 0; +} + +static void power_up_ldo12uhs(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); + +#ifdef BL808D_REWORK + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN_SEL, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 0); +#else + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 1); + BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); + arch_delay_us(300); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 6); +#endif + BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); + arch_delay_us(1); +} + +static void set_cen_ck_ckn(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + arch_delay_us(1); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); + tmpVal &= 0xFFFCFFFF; + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal); + arch_delay_us(1); +} + +static int set_or_uhs(uint32_t datarate) +{ + uint32_t tmpVal = 0; + uint32_t *uhs_phy_cfg_base_addr = (uint32_t *)(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_00_OFFSET); + // clang-format off + const static uint32_t uhs_phy_cfg_data[] ={ + 0x802b0200, 0x60206020, 0x70027002, 0x70027002, + 0x70027002, 0x70027002, 0x70027002, 0x70027002, + 0x70027002, 0x70027002, 0x26000000, 0x26000006, + }; + // clang-format on + + for (uint32_t i = 0; i < 12; i++) { + uhs_phy_cfg_base_addr[i] = uhs_phy_cfg_data[i]; + } + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30); + tmpVal &= 0x08ffffff; + tmpVal |= 0x07000000; + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30, tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48); + tmpVal &= 0xfffffcff; + tmpVal |= 0x00000200; + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48, tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C); + tmpVal &= 0xffe0ffff; + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C, tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal &= 0xff88ff88; + tmpVal |= 0x00330033; + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + arch_delay_us(1); + + return 0; +} +static void switch_to_ldo12uhs(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); + tmpVal &= 0xFFCFFFFF; + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal); + arch_delay_us(1); +} + +static void release_cen_ck_ckn(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); + tmpVal &= 0xFFFCFEFF; +#ifdef BL808D_REWORK + tmpVal |= 0x10000; +#else + tmpVal |= 0x30000; +#endif + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal); + arch_delay_us(1); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 3); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + arch_delay_us(1); +} + +static void Psram_analog_init(uint32_t pck_freq) +{ + /* power on ldo12 */ + power_up_ldo12uhs(); + + /* set cen ck ckn */ + set_cen_ck_ckn(); + + /* + * overwrite default register content + * only support 2000M and 1500MHZ + */ + set_or_uhs(pck_freq); + + /* switch to ldo12 */ + switch_to_ldo12uhs(); + + /* release cen ck */ + release_cen_ck_ckn(); + + /* config phy paramater */ + config_uhs_phy(pck_freq); +} + +/****************************************************************************/ /** + * @brief Init Psram UHS ,set auto refresh cycle + * + * @param cfg: pck frequency unit is MHZ + * + * @return None + * +*******************************************************************************/ +void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_PSRAM_UHS_MEM_SIZE_TYPE(cfg->psramMemSize)); + CHECK_PARAM(IS_PSRAM_UHS_PAGE_SIZE_TYPE(cfg->psramPageSize)); + + if (cfg->pck_freq > 2300) { + /* max support 2300MHZ */ + while (1) + ; + } else if (cfg->pck_freq > 1600) { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1a03000f); + } else { + BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1202000b); + } + + Psram_analog_init(cfg->pck_freq); + + /* Wait 150 us */ + arch_delay_us(150); + + /* set refresh paramater */ + /* 1. auto refresh clock source is pck_t, Adjust pck_t_div so that the frequency is around ~50Mhz */ + /* tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL); + tmpVal &= 0x00ffffff; + + if (cfg->pck_freq >= 2200) { + tmpVal |= 0x05000000; + } else if (cfg->pck_freq >= 2000) { + tmpVal |= 0x04000000; + } else if (cfg->pck_freq >= 1500) { + tmpVal |= 0x03000000; + } else if (cfg->pck_freq >= 1400) { + tmpVal |= 0x02000000; + } else if (cfg->pck_freq >= 666) { + tmpVal |= 0x01000000; + } + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal); */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL); + tmpVal &= 0x00ffffff; + + if (cfg->pck_freq >= 2200) { + tmpVal |= 0x05000000; + } else if (cfg->pck_freq >= 1800) { + tmpVal |= 0x04000000; + } else if (cfg->pck_freq >= 1500) { + tmpVal |= 0x03000000; + } else if (cfg->pck_freq >= 1400) { + tmpVal |= 0x02000000; + } else if (cfg->pck_freq >= 666) { + tmpVal |= 0x01000000; + } + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal); + + /* 2. setting refresh windows cycle count + * reg_win_cycle = refresh_window / Tpck_y + * + * refresh_window unit is ms + * when refresh tempotory > 85 + * refresh_window = 16 + * elsee + * refresh_window = 32 + */ + if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) { + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0x16e360); + } else { + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0xB71B0); + } + /* 3 & 4. setting refresh count in a windows fixed value 4096 in v0.2 + * calculate Average cycle between two auto-refresh + * reg_refi_cycle = reg_win_cycle / reg_win_ref_cnt + * */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_WIN_REF_CNT, 0x1000); + if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (370)); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (190)); + } + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2, tmpVal); + + /* 5 setting single auto refresh time */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, (uint32_t)(90 / T_pck_t)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, 5); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4, tmpVal); + + /* 6 auto-refesh enable */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_AF_EN); + + /* 7&8 . set psram memory size and page size */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_ADDRMB_MSK, cfg->psramMemSize); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_LINEAR_BND_B, cfg->psramPageSize); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 9. psram enable initial */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_INIT_EN); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); +} + +/****************************************************************************/ /** + * @brief Read register for uhs + * + * @param reg_addr: read addr + * @param regVal: regVal + * + * @return success or not + * +*******************************************************************************/ +int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal) +{ + uint32_t tmpVal = 0; + uint32_t cnt = 0; + + /* 1 generate requeset and wait authorization*/ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + return -1; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); + + /* 2 set mode reg */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, reg_addr); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 3 enable controller Rx*/ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGR_PULSE); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* 4 wait read done */ + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + return -1; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGR_DONE)); + + /* 5 steup up read data */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + + *regVal = (uint8_t)(BL_GET_REG_BITS_VAL(tmpVal, PSRAM_UHS_STS_CONFIG_READ)); + + /* 6 cancel requeset singnal */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + return 0; +} + +/****************************************************************************/ /** + * @brief write register for winbond PSRAM + * + * @param regCfg: wirte reg data + * + * @return None + * +*******************************************************************************/ +int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg) +{ + uint32_t tmpVal = 0; + uint32_t cnt = 0; + uint8_t regWriteList[] = { 0, 2 }; + uint8_t i = 0; + + CHECK_PARAM(IS_PSRAM_UHS_DRIVER_ST_TYPE(regCfg->driver_st)); + CHECK_PARAM(IS_PSRAM_UHS_WARP_BURST_TYPE(regCfg->burst_size)); + CHECK_PARAM(IS_PSRAM_UHS_LATENCY_TYPE(regCfg->lentency)); + + /* 1 congfi write reg*/ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE); + + switch (regCfg->burst_size) { + case PSRAM_UHS_WARP_BURST_64: + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16); + break; + case PSRAM_UHS_WARP_BURST_32: + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64); + break; + case PSRAM_UHS_WARP_BURST_16: + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64); + break; + case PSRAM_UHS_WARP_BURST_NONE: + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64); + break; + default: + return -1; + } + if (regCfg->driver_st != PSRAM_UHS_DRIVER_ST_NO_CHANGE) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DRIVE_ST, regCfg->driver_st); + } + if (regCfg->lentency != PSRAM_UHS_LATENCY_NO_CHANGE) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_LATENCY, regCfg->lentency); + } + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE, tmpVal); + + /* 2 generate requeset and wait authorization */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + return -1; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); + + for (i = 0; i < sizeof(regWriteList) / sizeof(uint8_t); i++) { + /* 3 set mode reg */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, regWriteList[i]); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 4 enable controller */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* 5 wait write done */ + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + return -1; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); + } + + /* 6 cancel requeset singnal */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + return 0; +} + +/****************************************************************************/ /** + * @brief Timing Reset + * + * @param reg_addr: reg_addr + * @param regCfg: wirte reg data + * + * @return None + * +*******************************************************************************/ +int PSram_UHS_Timing_Reset(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1); + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0); + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + arch_delay_us(1000); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 0); + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 4); + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal); + + return 0; +} + +/****************************************************************************/ /** + * @brief construct cmd wave for psram + * + * @param reg_addr: reg_addr + * @param regCfg: wirte reg data + * + * @return None + * +*******************************************************************************/ +int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd) +{ + uint32_t tmpVal = 0; + uint32_t cnt = 0; + + CHECK_PARAM(IS_PSRAM_UHS_CMD_TYPE(cmd)); + + /* generate requeset and wait authorization*/ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); + + /* enable cmd generate */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + + switch (cmd) { + case PSRAM_UHS_CMD_SELF_REFRESH_IN: + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFI_PULSE); + break; + case PSRAM_UHS_CMD_SELF_REFRESH_EXIT: + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFO_PULSE); + break; + case PSRAM_UHS_CMD_GLOBAL_RESET: + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_GLBR_PULSE); + /* Wait 15 us for reset */ + arch_delay_us(15); + break; + case PSRAM_UHS_CMD_ZQ_CAL_LONG: + + /* 3 set mode reg */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 5); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 4 enable controller */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* 5 wait write done */ + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); + + break; + case PSRAM_UHS_CMD_ZQ_CAL_SHORT: + + /* 3 set mode reg */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 6); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 4 enable controller */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* 5 wait write done */ + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); + break; + case PSRAM_UHS_CMD_ZQ_CAL_RESET: + + /* 3 set mode reg */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 7); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + /* 4 enable controller */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* 5 wait write done */ + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); + break; + default: + goto exit; + break; + } + + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal); + + cnt = 0; + + /* wait write done */ + switch (cmd) { + case PSRAM_UHS_CMD_SELF_REFRESH_IN: + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFI_DONE)); + break; + case PSRAM_UHS_CMD_SELF_REFRESH_EXIT: + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFO_DONE)); + break; + case PSRAM_UHS_CMD_GLOBAL_RESET: + do { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); + cnt++; + if (cnt > PSRAM_UHS_RW_TIMEOUT) + goto exit; + + } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_GLBR_DONE)); + break; + default: + goto exit; + } + + /* 6 cancel requeset singnal */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + return 0; + +exit: + /* 6 cancel requeset singnal */ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); + tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); + BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal); + + return -1; +} + +/** + * @brief defualt init for 64MB x16 UHS PSRAM + * user should enable UHS PSRAM PLL before call this function + * @param uhs_pll_clk The uhs pll frequency used + */ +void Psram_UHS_x16_Init(uint32_t uhs_pll_clk) +{ + PSRAM_UHS_Cfg_Type psramDefaultCfg = { + 2000, + PSRAM_MEM_SIZE_64MB, + PSRAM_PAGE_SIZE_2KB, + PSRAM_UHS_NORMAL_TEMP, + }; + + PSRAM_UHS_Write_Reg_Cfg_Type writeReg = { + PSRAM_UHS_DRIVER_ST_40_PDPU, + PSRAM_UHS_WARP_BURST_NONE, + PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, + }; + + psramDefaultCfg.pck_freq = uhs_pll_clk; + + if ((uhs_pll_clk >= 2000) && (uhs_pll_clk <= 2300)) { + writeReg.lentency = PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ; + } else if ((uhs_pll_clk <= 1600) && (uhs_pll_clk > 1066)) { + writeReg.lentency = PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ; + } else if ((uhs_pll_clk < 1067) && (uhs_pll_clk > 800)) { + writeReg.lentency = PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ; + } else if ((uhs_pll_clk <= 800) && (uhs_pll_clk > 667)) { + writeReg.lentency = PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ; + } else if ((uhs_pll_clk < 667) && (uhs_pll_clk > 400)) { + writeReg.lentency = PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ; + } else if (uhs_pll_clk <= 400) { + writeReg.lentency = PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ; + } + + /* first initial psram controller*/ + Psram_UHS_Init(&psramDefaultCfg); + + /* reset psram device*/ + PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_GLOBAL_RESET); + + arch_delay_us(100); + + /* write 1GHZ configuration to psram device */ + PSram_UHS_Write_Reg(&writeReg); +} + +void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg) +{ + /* first initial psram controller*/ + Psram_UHS_Init(cfg); + + uhs_phy_init(cfg); +} +/*@} end of group PSRAM_UHS_Public_Functions */ + +/*@} end of group PSRAM_UHS */ + +/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/ram/bflb/bl808_psram_uhs.h b/drivers/ram/bflb/bl808_psram_uhs.h new file mode 100644 index 00000000000..9440d676163 --- /dev/null +++ b/drivers/ram/bflb/bl808_psram_uhs.h @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file bl808_psram_uhs.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL808_PSRAM_UHS_H__ +#define __BL808_PSRAM_UHS_H__ + +#include +#include "bl808_common.h" + +/** @addtogroup BL808_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM_UHS + * @{ + */ + +/** @defgroup PSRAM_UHS_Public_Types + * @{ + */ + +/** + * @brief Psram UHS Size + */ +typedef enum { + PSRAM_MEM_SIZE_4MB = 0x03, /*!< PSRAM Memory Size 4M */ + PSRAM_MEM_SIZE_8MB = 0x07, /*!< PSRAM Memory Size 8M */ + PSRAM_MEM_SIZE_16MB = 0x0f, /*!< PSRAM Memory Size 16M */ + PSRAM_MEM_SIZE_32MB = 0x1f, /*!< PSRAM Memory Size 32M */ + PSRAM_MEM_SIZE_64MB = 0x3f, /*!< PSRAM Memory Size 64M */ +} PSRAM_UHS_Mem_Size_Type; + +/** + * @brief Psram UHS Page Type + */ +typedef enum { + PSRAM_PAGE_SIZE_2KB = 0x0B, /*!< PSRAM Page Size 2KB */ + PSRAM_PAGE_SIZE_4KB = 0x16, /*!< PSRAM Page Size 4KB */ +} PSRAM_UHS_Page_Size_Type; + +/** + * @brief Psram UHS Burst Size + */ +typedef enum { + PSRAM_UHS_WARP_BURST_64, /*!< PSRAM Warp Burst Size 64 */ + PSRAM_UHS_WARP_BURST_32, /*!< PSRAM Warp Burst Size 32 */ + PSRAM_UHS_WARP_BURST_16, /*!< PSRAM Warp Burst Size 16 */ + PSRAM_UHS_WARP_BURST_NONE, /*!< PSRAM Warp Burst NONE */ + PSRAM_UHS_WARP_BURST_NO_CHANGE, /*!< Not change this value */ +} PSRAM_UHS_WARP_BURST_Type; + +/** + * @brief Psram UHS Driver Strength + */ +typedef enum { + PSRAM_UHS_DRIVER_ST_34P3_PDPU = 0x1, /*!< 34.3 PD/PU */ + PSRAM_UHS_DRIVER_ST_40_PDPU = 0x2, /*!< 40 PD/PU */ + PSRAM_UHS_DRIVER_ST_48_PDPU = 0x3, /*!< 48 PD/PU */ + PSRAM_UHS_DRIVER_ST_60_PDPU = 0x4, /*!< 60 PD/PU */ + PSRAM_UHS_DRIVER_ST_80_PDPU = 0x6, /*!< 80 PD/PU */ + PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU = 0x9, /*!< 34.3 PD & 40 PU */ + PSRAM_UHS_DRIVER_ST_40_PD_48_PU = 0xa, /*!< 40 PD & 48 PU */ + PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU = 0xb, /*!< 34.3 PD & 48 PU */ + PSRAM_UHS_DRIVER_ST_NO_CHANGE = 0xf, /*!< Not change this value */ +} PSRAM_UHS_DRIVER_ST_Type; + +/** + * @brief Psram UHS LATENCY + */ +typedef enum { + PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ, /*!< MAX freq. = 533 MHz / Write LATENCY=10 / Read LATENCY=20 */ + PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ, /*!< MAX freq. = 800 MHz / Write LATENCY=14 / Read LATENCY=29 */ + PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ, /*!< MAX freq. = 933 MHz / Write LATENCY=16 / Read LATENCY=33 */ + PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, /*!< MAX freq. = 1066 MHz / Write LATENCY=18 / Read LATENCY=37 */ + PSRAM_UHS_LATENCY_RESERVED, /*!< Reserved */ + PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ, /*!< MAX freq. = 400 MHz / Write LATENCY=6 / Read LATENCY=16 */ + PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ, /*!< MAX freq. = 333 MHz / Write LATENCY=5 / Read LATENCY=13 */ + PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ, /*!< MAX freq. = 200 MHz / Write LATENCY=5 / Read LATENCY=9 */ + PSRAM_UHS_LATENCY_NO_CHANGE, /*!< Not change this value */ +} PSRAM_UHS_LATENCY_Type; + +/** + * @brief Psram UHS CMD Type + */ +typedef enum { + PSRAM_UHS_CMD_SELF_REFRESH_IN, /*!< pSRAM self-refresh in command */ + PSRAM_UHS_CMD_SELF_REFRESH_EXIT, /*!< pSRAM self-refresh exit command */ + PSRAM_UHS_CMD_GLOBAL_RESET, /*!< pSRAM global reset command */ + PSRAM_UHS_CMD_ZQ_CAL_LONG, /*! */ + PSRAM_UHS_CMD_ZQ_CAL_SHORT, /*!*/ + PSRAM_UHS_CMD_ZQ_CAL_RESET, /*!*/ +} PSRAM_UHS_CMD_Type; + +/** + * @brief PSRAM UHS Temperature + * + */ +typedef enum { + PSRAM_UHS_NORMAL_TEMP, + PSRAM_UHS_HIGH_TEMP, +} PSRAM_UHS_TEMP_Type; + +/** + * @brief PSRAM_UHS_Cfg_Type + */ +typedef struct { + uint32_t pck_freq; /*!< pck frequency unit is MHZ */ + PSRAM_UHS_Mem_Size_Type psramMemSize; /*!< psram uhm memory size */ + PSRAM_UHS_Page_Size_Type psramPageSize; /*!< psram uhm page size */ + PSRAM_UHS_TEMP_Type isHighTem; /*!< auto refresh work temperature */ +} PSRAM_UHS_Cfg_Type; + +/** + * @brief PSRAM_UHS_Phy_Latency_Pra_Type + */ +typedef struct { + uint8_t phy_rl_ana; /*!< phy_rl_ana */ + uint8_t phy_rl_dig; /*!< phy_rl_dig*/ + uint8_t phy_wl_ana; /*!< phy_wl_ana */ + uint8_t phy_wl_dig; /*!< phy_wl_dig*/ + uint8_t phy_wl_dq_ana; /*!< phy_wl_dq_ana */ + uint8_t phy_wl_dq_dig; /*!< phy_wl_dq_dig */ + + uint8_t reg_timer_array_read; /*!< reg_timer_array_read */ + uint8_t reg_timer_array_write; /*!< reg_timer_array_write */ + uint8_t reg_timer_dqs_array_stop; /*!< reg_timer_dqs_array_stop */ + uint8_t reg_timer_dqs_start; /*!< reg_timer_dqs_start */ + + uint8_t reg_timer_dqs_stop; /*!< reg_timer_dqs_stop */ + uint8_t reg_timer_reg_read; /*!< reg_timer_reg_read */ + uint8_t reg_timer_reg_write; /*!< reg_timer_reg_write */ + uint8_t reg_timer_auto_refresh; /*!< reg_timer_auto_refresh */ + + uint16_t reg_timer_global_rst; /*!< reg_timer_global_rst */ + uint8_t reg_timer_self_refresh1_in; /*!< reg_timer_self_refresh1_in */ + uint8_t reg_timer_self_refresh1_exit; /*!< reg_timer_self_refresh1_exit */ + + uint8_t reg_timer_reg_write_busy; /*!< reg_timer_reg_write_busy */ + uint8_t reg_timer_reg_read_busy; /*!< reg_timer_reg_read_busy */ + uint8_t reg_timer_arrary_write_busy; /*!< reg_timer_arrary_write_busy */ + uint8_t reg_timer_arrary_read_busy; /*!< reg_timer_arrary_read_busy */ + + uint8_t en_rx_fe_dly; /*!< en_rx_fe_dly */ + uint8_t odt_sel_dly; /*!< odt_sel_dly */ + + uint8_t reg_trc_cycle; /*!< reg_trc_cycle */ + uint8_t reg_trfc_cycle; /*!< reg_trfc_cycle */ + uint8_t reg_tcphr_cycle; /*!< reg_tcphr_cycle */ + uint8_t reg_tcphw_cycle; /*!< reg_tcphw_cycle */ + +} PSRAM_UHS_Phy_Latency_Pra_Type; + +/** + * @brief PSRAM_UHS_Write_Reg_Cfg_Type + */ +typedef struct { + PSRAM_UHS_DRIVER_ST_Type driver_st; /*!< driver strength */ + PSRAM_UHS_WARP_BURST_Type burst_size; /*!< burst size */ + PSRAM_UHS_LATENCY_Type lentency; /*!< lentency */ +} PSRAM_UHS_Write_Reg_Cfg_Type; + +/*@} end of group PSRAM_UHS_Public_Types */ + +/** @defgroup PSRAM_UHS_Public_Constants + * @{ + */ + +/** @defgroup PSRAM_UHS_MEM_SIZE_TYPE + * @{ + */ +#define IS_PSRAM_UHS_MEM_SIZE_TYPE(type) (((type) == PSRAM_MEM_SIZE_4MB) || \ + ((type) == PSRAM_MEM_SIZE_8MB) || \ + ((type) == PSRAM_MEM_SIZE_16MB) || \ + ((type) == PSRAM_MEM_SIZE_32MB)) + +/** @defgroup PSRAM_UHS_PAGE_SIZE_TYPE + * @{ + */ +#define IS_PSRAM_UHS_PAGE_SIZE_TYPE(type) (((type) == PSRAM_PAGE_SIZE_2KB) || \ + ((type) == PSRAM_PAGE_SIZE_4KB)) + +/** @defgroup PSRAM_UHS_WARP_BURST_TYPE + * @{ + */ +#define IS_PSRAM_UHS_WARP_BURST_TYPE(type) (((type) == PSRAM_UHS_WARP_BURST_64) || \ + ((type) == PSRAM_UHS_WARP_BURST_32) || \ + ((type) == PSRAM_UHS_WARP_BURST_16)) + +/** @defgroup PSRAM_UHS_DRIVER_ST_TYPE + * @{ + */ +#define IS_PSRAM_UHS_DRIVER_ST_TYPE(type) (((type) == PSRAM_UHS_DRIVER_ST_34P3_PUPU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_40_PUPU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_48_PUPU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_60_PUPU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_80_PUPU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_40_PD_48_PU) || \ + ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU)) + +/** @defgroup PSRAM_UHS_LATENCY_TYPE + * @{ + */ +#define IS_PSRAM_UHS_LATENCY_TYPE(type) (((type) == PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ) || \ + ((type) == PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ)) +/** @defgroup PSRAM_UHS_CMD_Type + * @{ + */ +#define IS_PSRAM_UHS_CMD_TYPE(type) (((type) == PSRAM_UHS_CMD_SELF_REFRESH_IN) || \ + ((type) == PSRAM_UHS_CMD_SELF_REFRESH_EXIT) || \ + ((type) == PSRAM_UHS_CMD_GLOBAL_RESET) + +/*@} end of group PSRAM_UHS_Public_Constants */ + +/** @defgroup PSRAM_UHS_Public_Macros + * @{ + */ + +/*@} end of group PSRAM_UHS_Public_Macros */ + +/** @defgroup PSRAM_UHS_Public_Functions + * @{ + */ +void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg); +int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal); +int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg); +int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd); +void Psram_UHS_x16_Init(uint32_t uhs_pll_clk); +void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg); +/*@} end of group PSRAM_UHS_Public_Functions */ + +/*@} end of group PSRAM_UHS */ + +/*@} end of group BL808_Peripheral_Driver */ + +#endif /* __BL808_PSRAM_UHS_H__ */ diff --git a/drivers/ram/bflb/bl808_uhs_phy.c b/drivers/ram/bflb/bl808_uhs_phy.c new file mode 100644 index 00000000000..8450df7c9ea --- /dev/null +++ b/drivers/ram/bflb/bl808_uhs_phy.c @@ -0,0 +1,2780 @@ +#include "bl808_uhs_phy.h" +#include +#include +#include +#include +#include +#include + +#define bl808_DBG_RF (0) // 0 is for commit with only err log, 1 is for all debug log, 2 is for key debug log +#if bl808_DBG_RF == 1 + #define uhs_phy_printf_debug printf // debug mode + #define uhs_phy_printf printf + #define uhs_phy_printfe printf +#elif bl808_DBG_RF == 2 + #define uhs_phy_printf_debug(...) + #define uhs_phy_printf printf // commit it out in release version, use to collect data + // #define uhs_phy_printf(...) // used in release version + #define uhs_phy_printfe printf +#else + #define uhs_phy_printf_debug(...) + #define uhs_phy_printf(...) + #define uhs_phy_printfe printf +#endif + +#define ODT_EN (0) +// #define PSRAM_32MB (0) +#define CACHE_EN (0) // unused ! + +static uhs_phy_cal_res_struct cal_res; +uhs_phy_cal_res_struct* uhs_phy_cal_res = &cal_res; +static uint8_t err_flag = 0; +#define CHECK_ERR_FLAG(func,args) {\ + func args;\ + if(err_flag)return err_flag;\ +} + +static uint8_t uhs_latency_code = 1; +static uint32_t dqs_dq_delta = 0; +static uint8_t regr_done_err = 0; +static uint8_t reg_read_err = 0; +static uint8_t reg_write_err = 0; +static uint8_t init_array_write_err = 0; +static uint8_t array_read_err = 0; +static uint32_t addr_dump = 0x3000F000; +// +static uint32_t addr_rarray = 0x50000000; +static uint32_t data0_rarray = 0x12345678; +static uint32_t data1_rarray = 0x87654321; +// uint32_t datarate_glb; +static uint32_t latency_wr[2] = {9,30}; +static PSRAM_UHS_Cfg_Type *cfg_glb; +// static uint32_t addr_sr[3] = {0x3000f014,0x3000f018,0x3000f020}; +// static uint32_t val_sr[3] = {0x0,0x0,0x0}; +static uint32_t latency_wr_2kM[2] = {13,41}; +static uint8_t cal_done_flag = 0; +static uint8_t print_flag = 0; +// static uint32_t latency_wr_2kM_init[2] = {13,36}; +static uint8_t flag_ck1 = 0; +static uint8_t flag_ck2 = 0; + +void set_uhs_latency_w(uint32_t uhs_latency); +void set_uhs_latency_r(uint32_t uhs_latency); +void uhs_reset(uint8_t ma_rb); +void uhs_phy_reg_dump(void); +void set_or_uhs(void); +uint8_t mr_read_back(void); +uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg); + +void uhs_phy_delay_us(uint32_t us) +{ + arch_delay_us(us); +} + +void uhs_phy_delay_ms(uint32_t ms) +{ + arch_delay_us(1000 * ms); +} + +void uhs_phy_af_reg(uint32_t REG_PCK_T_DIV,uint32_t REG_WIN_CYCLE,uint32_t REG_WIN_REF_CNT,uint32_t REG_REFI_CYCLE,uint32_t REG_BUST_CYCLE) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,REG_PCK_T_DIV); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,REG_WIN_CYCLE); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,REG_WIN_REF_CNT); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,REG_REFI_CYCLE); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,REG_BUST_CYCLE); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); +} + +void uhs_phy_af_onoff(uint8_t onoff){ + uint32_t tmpVal = 0; + + if(onoff){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(50); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + // uhs_phy_delay_us(50); + }else{ + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x0); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + // uhs_phy_delay_us(50); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(50); + } +} + +void uhs_phy_af_cfg(void) +{ + // uint32_t tmpVal = 0; + + uhs_phy_af_onoff(0); + + if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){ + if(cfg_glb->pck_freq == 2000){ + uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x6); + } + else if(cfg_glb->pck_freq == 1900){ + uhs_phy_af_reg(0x4,0xE7EEF,0x2000,0x72,0x6); + } + else if(cfg_glb->pck_freq == 1800){ + uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x6); + } + else if(cfg_glb->pck_freq == 1700){ + uhs_phy_af_reg(0x4,0xCF84F,0x2000,0x66,0x5); + } + else if(cfg_glb->pck_freq == 1600){ + uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x5); + } + else if(cfg_glb->pck_freq == 1500){ + uhs_phy_af_reg(0x4,0xB71AF,0x2000,0x5A,0x5); + } + else if(cfg_glb->pck_freq == 1400){ + uhs_phy_af_reg(0x4,0xAAE5F,0x2000,0x54,0x4); + } + else if(cfg_glb->pck_freq == 1300){ + uhs_phy_af_reg(0x4,0x9EB0F,0x2000,0x4E,0x4); + } + else if(cfg_glb->pck_freq == 1200){ + uhs_phy_af_reg(0x4,0x927BF,0x2000,0x48,0x4); + } + else if(cfg_glb->pck_freq == 1100){ + uhs_phy_af_reg(0x4,0x8646F,0x2000,0x42,0x4); + } + else if(cfg_glb->pck_freq == 1000){ + uhs_phy_af_reg(0x4,0x7A11F,0x2000,0x3C,0x3); + } + else if(cfg_glb->pck_freq == 900){ + uhs_phy_af_reg(0x4,0x6DDCF,0x2000,0x35,0x3); + } + else{ + uhs_phy_af_reg(0x4,0x61A7F,0x2000,0x2F,0x3); + } + } + else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + if(cfg_glb->pck_freq == 2000){ + uhs_phy_af_reg(0x4,0x1E847F,0x2000,0xF3,0x6); + } + else if(cfg_glb->pck_freq == 1900){ + uhs_phy_af_reg(0x4,0x1CFDDF,0x2000,0xE6,0x6); + } + else if(cfg_glb->pck_freq == 1800){ + uhs_phy_af_reg(0x4,0x1B773F,0x2000,0xDA,0x6); + } + else if(cfg_glb->pck_freq == 1700){ + uhs_phy_af_reg(0x4,0x19F09F,0x2000,0xCE,0x5); + } + else if(cfg_glb->pck_freq == 1600){ + uhs_phy_af_reg(0x4,0x1869FF,0x2000,0xC2,0x5); + } + else if(cfg_glb->pck_freq == 1500){ + uhs_phy_af_reg(0x4,0x16E35F,0x2000,0xB6,0x5); + } + else if(cfg_glb->pck_freq == 1400){ + uhs_phy_af_reg(0x4,0x155CBF,0x2000,0xA9,0x4); + } + else if(cfg_glb->pck_freq == 1300){ + uhs_phy_af_reg(0x4,0x13D61F,0x2000,0x9D,0x4); + } + else if(cfg_glb->pck_freq == 1200){ + uhs_phy_af_reg(0x4,0x124F7F,0x2000,0x91,0x4); + } + else if(cfg_glb->pck_freq == 1100){ + uhs_phy_af_reg(0x4,0x10C8DF,0x2000,0x85,0x4); + } + else if(cfg_glb->pck_freq == 1000){ + uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x3); + } + else if(cfg_glb->pck_freq == 900){ + uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x3); + } + else{ + uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x3); + } + } + else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){ + if(cfg_glb->pck_freq == 2000){ + uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x6); + } + else if(cfg_glb->pck_freq == 1900){ + uhs_phy_af_reg(0x4,0xE7EEF,0x1000,0xE6,0x6); + } + else if(cfg_glb->pck_freq == 1800){ + uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x6); + } + else if(cfg_glb->pck_freq == 1700){ + uhs_phy_af_reg(0x4,0xCF84F,0x1000,0xCE,0x5); + } + else if(cfg_glb->pck_freq == 1600){ + uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x5); + } + else if(cfg_glb->pck_freq == 1500){ + uhs_phy_af_reg(0x4,0xB71AF,0x1000,0xB6,0x5); + } + else if(cfg_glb->pck_freq == 1400){ + uhs_phy_af_reg(0x4,0xAAE5F,0x1000,0xA9,0x4); + } + else if(cfg_glb->pck_freq == 1300){ + uhs_phy_af_reg(0x4,0x9EB0F,0x1000,0x9D,0x4); + } + else if(cfg_glb->pck_freq == 1200){ + uhs_phy_af_reg(0x4,0x927BF,0x1000,0x91,0x4); + } + else if(cfg_glb->pck_freq == 1100){ + uhs_phy_af_reg(0x4,0x8646F,0x1000,0x85,0x4); + } + else if(cfg_glb->pck_freq == 1000){ + uhs_phy_af_reg(0x4,0x7A11F,0x1000,0x79,0x3); + } + else if(cfg_glb->pck_freq == 900){ + uhs_phy_af_reg(0x4,0x6DDCF,0x1000,0x6C,0x3); + } + else{ + uhs_phy_af_reg(0x4,0x61A7F,0x1000,0x60,0x3); + } + } + else{ + if(cfg_glb->pck_freq == 2000){ + uhs_phy_af_reg(0x4,0x1E847F,0x1000,0x1E7,0x6); + } + else if(cfg_glb->pck_freq == 1900){ + uhs_phy_af_reg(0x4,0x1CFDDF,0x1000,0x1CE,0x6); + } + else if(cfg_glb->pck_freq == 1800){ + uhs_phy_af_reg(0x4,0x1B773F,0x1000,0x1B6,0x6); + } + else if(cfg_glb->pck_freq == 1700){ + uhs_phy_af_reg(0x4,0x19F09F,0x1000,0x19E,0x5); + } + else if(cfg_glb->pck_freq == 1600){ + uhs_phy_af_reg(0x4,0x1869FF,0x1000,0x185,0x5); + } + else if(cfg_glb->pck_freq == 1500){ + uhs_phy_af_reg(0x4,0x16E35F,0x1000,0x16D,0x5); + } + else if(cfg_glb->pck_freq == 1400){ + uhs_phy_af_reg(0x4,0x155CBF,0x1000,0x154,0x4); + } + else if(cfg_glb->pck_freq == 1300){ + uhs_phy_af_reg(0x4,0x13D61F,0x1000,0x13C,0x4); + } + else if(cfg_glb->pck_freq == 1200){ + uhs_phy_af_reg(0x4,0x124F7F,0x1000,0x123,0x4); + } + else if(cfg_glb->pck_freq == 1100){ + uhs_phy_af_reg(0x4,0x10C8DF,0x1000,0x10B,0x4); + } + else if(cfg_glb->pck_freq == 1000){ + uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x3); + } + else if(cfg_glb->pck_freq == 900){ + uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x3); + } + else{ + uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x3); + } + } + + uhs_phy_af_onoff(1); +} + +void Psram_UHS_Init_Override(PSRAM_UHS_Cfg_Type *cfg){ + uint32_t tmpVal = 0; + + Psram_UHS_Init(cfg); + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + } + + #if CAL_MODE == 1 + uhs_phy_af_cfg(); + #endif + + set_or_uhs(); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 5); + BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); + uhs_phy_printf("GLB_LDO12UHS: %x\r\n",tmpVal); + uhs_phy_delay_us(250); +} + +void power_up_mm(uint8_t off) +{ + uint32_t tmpVal = 0; + if (off == 0) + { + // power up MM domain + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(150); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + // uhs_phy_delay_us(10); + // uhs_phy_delay_ms(1); + } + else + { + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + uhs_phy_delay_us(150); + tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off); + BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); + } + uhs_phy_delay_us(100); +} + +void power_up_uhspll(void) +{ + // power_up_uhspll + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1); + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x0); + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); + uhs_phy_delay_us(50); + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x1); + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); + uhs_phy_delay_us(50); + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0); + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); + uhs_phy_delay_us(50); + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1); + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); + uhs_phy_delay_us(50); +} + +void power_up_ldo12uhs(void) +{ + // use internal LDO + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5); + BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); + uhs_phy_delay_us(200); + // use external LDO + // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); + // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); +} + +void set_cen_ck_ckn(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); + uhs_phy_delay_us(10); +} + +void set_or_uhs(void) +{ + uint32_t tmpVal = 0; + + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + } + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); + uhs_phy_delay_us(200); +} + +void switch_to_ldo12uhs(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); + uhs_phy_delay_us(200); +} + +void release_cen_ck_ckn(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); + uhs_phy_delay_us(10); +} + +void uhs_phy_pwr_down(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0); + BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); + uhs_phy_delay_us(100); + tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); + BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); + uhs_phy_delay_us(100); + tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0); + BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); + uhs_phy_delay_us(100); +} + +void psram_init(void) +{ + uint8_t i; + uint32_t tmpVal = 0; + for (i = 0; i < 1; i++){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram + // }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram + // } + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); + uhs_phy_delay_us(100); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(100); + } + + // // psram auto refresh at 2000Mbps + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + + // // psram cmd timing < 2000Mbps + // BL_WR_WORD(0x3000F030,0x18090610); +} + +void set_uhs_phy_init(void) +{ + // set phy & controller + uint32_t tmpVal = 0; + // default latency(800MHz) + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7); + // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x1); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2); + // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x2); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x05000501); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x02080108); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x03e90b0b); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x040b0308); + }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c); + } + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); + uhs_phy_delay_us(100); +} + +void set_uhs_phy(void) +{ + uint32_t tmpVal = 0; + // set phy & controller + // latency code=3 (1066MHz) + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323); // if fail than use 0x0f391323 + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); // tDQSS -> -1 + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a3233); // tDQSS -> 1 + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + set_uhs_latency_w(latency_wr[0]); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333); + + uhs_phy_delay_us(100); +} + +uint8_t uhs_err_handler(uint8_t err) +{ + err_flag = 1; + uhs_phy_cal_res->err_type = err; + switch (err) { + case UHS_REGR_GNT_ERR: + uhs_phy_printfe("UHS_REGR_GNT_ERR\r\n"); + break; + case UHS_REGR_DONE_ERR: + uhs_phy_printfe("UHS_REGR_DONE_ERR = %d\r\n",regr_done_err); + uhs_phy_cal_res->err_sub_type = regr_done_err; + break; + case UHS_REGW_GNT_ERR: + uhs_phy_printfe("UHS_REGW_GNT_ERR\r\n"); + break; + case UHS_REGW_DONE_ERR: + uhs_phy_printfe("UHS_REGW_DONE_ERR\r\n"); + break; + case UHS_LATENCY_CODE_WRITE_ERR: + uhs_phy_printfe("UHS_LATENCY_CODE_WRITE_ERR\r\n"); + break; + case UHS_INIT_ARRAY_WRITE_ERR: + uhs_phy_printfe("UHS_INIT_ARRAY_WRITE_ERR = %d\r\n",init_array_write_err); + uhs_phy_cal_res->err_sub_type = init_array_write_err; + break; + case UHS_REG_READ_CAL_ERR: + uhs_phy_printfe("UHS_REG_READ_CAL_ERR = %d\r\n",reg_read_err); + uhs_phy_cal_res->err_sub_type = reg_read_err; + break; + case UHS_REG_WRITE_CAL_ERR: + uhs_phy_printfe("UHS_REG_WRITE_CAL_ERR = %d\r\n",reg_write_err); + uhs_phy_cal_res->err_sub_type = reg_write_err; + break; + case UHS_ARRAY_READ_LAT_ERR: + uhs_phy_printfe("UHS_ARRAY_READ_LAT_ERR = %d\r\n",array_read_err); + uhs_phy_cal_res->err_sub_type = array_read_err; + break; + case UHS_ARRAY_WRITE_CK_ERR: + uhs_phy_printfe("UHS_ARRAY_WRITE_CK_ERR\r\n"); + break; + case UHS_ARRAY_READ_CAL_ERR: + uhs_phy_printfe("UHS_ARRAY_READ_CAL_ERR\r\n"); + break; + case UHS_ARRAY_WRITE_CAL_ERR: + uhs_phy_printfe("UHS_ARRAY_WRITE_CAL_ERR\r\n"); + break; + case UHS_CACHE_ENABLE_ERR: + uhs_phy_printfe("UHS_CACHE_ENABLE_ERR\r\n"); + break; + case UHS_CACHE_DISABLE_ERR: + uhs_phy_printfe("UHS_CACHE_DISABLE_ERR\r\n"); + break; + case UHS_CACHE_RECOVER_ERR: + uhs_phy_printfe("UHS_CACHE_RECOVER_ERR\r\n"); + break; + case UHS_REG_WRITE_2kM_ERR: + uhs_phy_printfe("UHS_REG_WRITE_2kM_ERR\r\n"); + break; + case UHS_BAD_DIE_ERR: + uhs_phy_printfe("UHS_BAD_DIE_ERR\r\n"); + break; + case UHS_DIAGONAL_TEST_ERR: + uhs_phy_printfe("UHS_DIAGONAL_TEST_ERR\r\n"); + break; + case UHS_ALL_ADDR_TEST_ERR: + uhs_phy_printfe("UHS_ALL_ADDR_TEST_ERR\r\n"); + break; + default: + break; + } + uhs_phy_printfe("ERR_AT %dMbps\r\n",cfg_glb->pck_freq); + uhs_phy_reg_dump(); + #if CAL_MODE == 0 || CAL_MODE == 1 + while(1){ + uhs_phy_printfe("%d",err); + uhs_phy_delay_ms(10000); + }; + #endif + return err_flag; +} + +void uhs_phy_reg_dump(void){ + uint32_t len = 0x150; + uint32_t i = 0; + + // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_START\r\n"); + // for(i = 0;i <= len;i = i+4){ + // uhs_phy_printf_debug("0x%x,0x%x\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i))); + // } + // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_END\r\n"); + uhs_phy_printfe("UHS_PHY_REG_DUMP_START\r\n"); + for(i = 0;i <= len;i = i+4){ + uhs_phy_printfe("0x%x,0x%x\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i))); + } + uhs_phy_printfe("UHS_PHY_REG_DUMP_END\r\n"); +} + +uint8_t uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32) +{ + uint32_t tmpVal = 0; + uint32_t count = 0; + if(ma == 0) + { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); + } + else if(ma == 2) + { + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); + if (BL_32 == 1){ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0); + }else if (BL_32 == 2){ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x1); + }else{ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0); + } + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); + } + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + // uhs_phy_printf_debug("reg_w GNT while\r\n"); + while (1) + { + if (count == 100000){ + return uhs_err_handler(UHS_REGW_GNT_ERR); + } + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); + if (tmpVal == 1) + { + uhs_phy_printf_debug("reg_w GNT pass\r\n"); + break; + } + count ++; + } + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); + + count = 0; + while (1) + { + if (count == 100000){ + return uhs_err_handler(UHS_REGW_DONE_ERR); + } + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGW_DONE); //regw_done + if (tmpVal == 1) + { + uhs_phy_printf_debug("reg_w DONE pass\r\n"); + break; + } + count ++; + } + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(10); + + return 0; +} + +uint8_t uhs_reg_r(uint32_t ma,uint8_t flag) +{ + uint32_t tmpVal = 0; + // uint32_t tmpInd = 0; + uint32_t count = 0; + uint8_t opc = 1; + + if (flag == 1){ + uhs_phy_af_onoff(0); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x1); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + uhs_phy_delay_us(50); + } + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + + while (1) + { + if (count == 100000){ + return uhs_err_handler(UHS_REGR_GNT_ERR); + } + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); + if (tmpVal == 1) + { + uhs_phy_printf_debug("reg_r GNT pass\r\n"); + break; + } + count ++; + } + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1); //reg_regr_pulse + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); + + count = 0; + while (1) + { + if (flag == 1){ + if (count == 100){ + regr_done_err = 2; + return uhs_err_handler(UHS_REGR_DONE_ERR); + } + uhs_phy_delay_us(20); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done + if (tmpVal == 1){ + uhs_phy_printf_debug("reg_r DONE pass\r\n"); + break; + } + count ++; + + // if (tmpVal == 1){ + // uhs_phy_printf_debug("reg_r DONE pass\r\n"); + // opc = 1; + // }else{ + // uhs_phy_printf_debug("reg_r DONE fail\r\n"); + // opc = 0; + // } + // break; + } + else{ + if (count == 100000){ + regr_done_err = 1; + return uhs_err_handler(UHS_REGR_DONE_ERR); + } + uhs_phy_delay_us(10); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done + if (tmpVal == 1){ + uhs_phy_printf_debug("reg_r DONE pass\r\n"); + break; + } + count ++; + } + } + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + + if (opc == 0){ + uhs_reset(0); + } + + if (flag == 1){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x0); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); + uhs_phy_delay_us(50); + + uhs_phy_af_onoff(1); + } + + uhs_phy_delay_us(10); + return opc; +} + + +void cfg_dq_rx(uint8_t dq){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); + uhs_phy_delay_us(10); +} + +void cfg_dqs_rx(uint8_t dqs){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); + uhs_phy_delay_us(10); +} + +void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); + uhs_phy_delay_us(50); +} + +void uhs_reset(uint8_t ma_rb) +{ + // uint32_t tmpVal = 0; + // uint32_t len = 0x150; + // uint32_t val_sr[len>>2]; + // int32_t i = 0; + + uhs_phy_printf("IN_UHS_RESET\r\n"); + + // for( i = len ; i >= 0 ; i = i-4 ){ + // if( i != 0x4 ){ + // val_sr[i>>2] = *((volatile uint32_t*)(addr_dump + i)); + // } + // } + + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0); + // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + // uhs_phy_delay_us(100); + + // tmpVal = BL_RD_WORD(0x30007044); + // tmpVal = tmpVal | 0x00008000; + // BL_WR_WORD(0x30007044,tmpVal); + // uhs_phy_delay_us(100); + // tmpVal = tmpVal & 0xFFFF7FFF; + // BL_WR_WORD(0x30007044,tmpVal); + // uhs_phy_delay_us(200); + + // BL_WR_WORD(0x3000F030,0x18090610); + + // #if PSRAM_32MB + // PSRAM_UHS_Cfg_Type psramCfg = { + // datarate, + // PSRAM_MEM_SIZE_32MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + // #else + // PSRAM_UHS_Cfg_Type psramCfg = { + // datarate, + // PSRAM_MEM_SIZE_64MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + // #endif + // Psram_UHS_Init_Override(cfg_glb); //controller init + + // set_or_uhs(); + // set_uhs_phy(); + + // for( i = len ; i >= 0 ; i = i-4 ){ + // if( i != 0x4 ){ + // *((volatile uint32_t*)(addr_dump + i)) = val_sr[i>>2]; + // } + // } + // uhs_phy_delay_us(400); + + if (ma_rb){ + mr_read_back(); + }else{ + power_up_mm(1); + uhs_phy_pwr_down(); + latency_wr_2kM[1] --; + uhs_phy_init_core(cfg_glb); + } + + uhs_phy_printf("OUT_UHS_RESET\r\n"); +} + +void set_uhs_latency_r(uint32_t uhs_latency) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + uhs_phy_delay_us(50); +} + +void set_uhs_latency_w(uint32_t uhs_latency) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,uhs_latency%4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,uhs_latency/4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,(uhs_latency+1)%4); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,(uhs_latency+1)/4); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + uhs_phy_delay_us(50); +} + +uint8_t mr_read_back(void) +{ + uint8_t cnt1; + uint32_t tmpVal; + for (cnt1=0;cnt1<=4;cnt1++){ + if(cnt1 != 3){ + CHECK_ERR_FLAG(uhs_reg_r,(cnt1,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf("MA%d = 0x%x\r\n",cnt1,tmpVal); + } + } + return 0; +} + +uint8_t reg_read_cal(void) +{ + uint32_t tmpVal = 0; + uint32_t tmpVal_1 = 1; + uint32_t uhs_latency = 42; + int32_t i = 0; + uint8_t dqs_dq_flag = 0; + uint32_t reg_dqs = 0; + uint32_t reg_dq = 0; + + // for(uhs_latency = 41; uhs_latency > 0; uhs_latency --) + for(uhs_latency = latency_wr_2kM[1]; uhs_latency > 0; uhs_latency --) + { + if(uhs_latency == 34) + { + reg_read_err = 1; + return uhs_err_handler(UHS_REG_READ_CAL_ERR); + } + uhs_phy_printf_debug("reg read cal 1st by latency= %d\r\n",uhs_latency); + set_uhs_latency_r(uhs_latency); + + // sweep dqs + cfg_dq_rx(0); + for(i = 15; i >= 0; i --) + { + cfg_dqs_rx(i); + // tmpVal_1 = uhs_reg_r(0,1); + CHECK_ERR_FLAG(uhs_reg_r,(0,1)); + if (cal_done_flag == 1) + return 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dqs--, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){ + uhs_phy_printf_debug("reg read pass by dqs= %d\r\n",i); + // reg_dqs = i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dqs= %d\r\n",i); + } + // if(tmpVal_1 == 0){ + // uhs_phy_printf_debug("read done not found!!!\r\n"); + // // uhs_reset(datarate); + // set_uhs_latency_r(uhs_latency); + // cfg_dq_rx(0); + // } + } + + // sweep dq + cfg_dqs_rx(0); + for(i = 15; i >=0; i --) + { + cfg_dq_rx(i); + // tmpVal_1 = uhs_reg_r(0,1); + CHECK_ERR_FLAG(uhs_reg_r,(0,1)); + if (cal_done_flag == 1) + return 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dq--, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){ + uhs_phy_printf_debug("reg read pass by dq= %d\r\n",i); + // reg_dq = i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dq= %d\r\n",i); + } + // if(tmpVal_1 == 0){ + // uhs_phy_printf_debug("read done not found!!!\r\n"); + // // uhs_reset(datarate); + // set_uhs_latency_r(uhs_latency); + // cfg_dqs_rx(0); + // } + } + if (dqs_dq_flag == 1){ + dqs_dq_flag = 0; + + uhs_latency = uhs_latency - 2; + uhs_phy_printf_debug("reg read cal 2nd by latency= %d\r\n",uhs_latency); + set_uhs_latency_r(uhs_latency); //got a good robust uhs_latency + latency_wr[1] = uhs_latency; + //******verify the uhs_latency and get dqs/dq timing + //sweep dqs + cfg_dq_rx(0); + for(i = 15; i >= 0; i --) + { + cfg_dqs_rx(i); + CHECK_ERR_FLAG(uhs_reg_r,(0,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs--, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)) + { + uhs_phy_printf("reg read pass by --dqs= %d\r\n",i); + reg_dqs += i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dqs= %d\r\n",i); + } + } + for(i = 0; i <= 15; i ++) + { + cfg_dqs_rx(i); + CHECK_ERR_FLAG(uhs_reg_r,(0,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs++, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)) + { + uhs_phy_printf("reg read pass by ++dqs= %d\r\n",i); + reg_dqs += i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dqs= %d\r\n",i); + } + } + // sweep dq + cfg_dqs_rx(0); + for(i = 15; i >= 0; i --) + { + cfg_dq_rx(i); + CHECK_ERR_FLAG(uhs_reg_r,(0,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq--, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)) + { + uhs_phy_printf("reg read pass by --dq= %d\r\n",i); + reg_dq += i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dq= %d\r\n",i); + } + } + for(i = 0; i <= 15; i ++) + { + cfg_dq_rx(i); + CHECK_ERR_FLAG(uhs_reg_r,(0,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq++, 0x%x\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)) + { + uhs_phy_printf("reg read pass by ++dq= %d\r\n",i); + reg_dq += i; + dqs_dq_flag = 1; + break; + } + else{ + uhs_phy_printf_debug("reg read fail by dq= %d\r\n",i); + } + } + + if(dqs_dq_flag == 0) + { + reg_read_err = 2; + return uhs_err_handler(UHS_REG_READ_CAL_ERR); + } + + if(reg_dqs >= reg_dq) + { + reg_dqs = (reg_dqs-reg_dq)/2; + reg_dq = 0; + } + else + { + reg_dq = (reg_dq-reg_dqs)/2; + reg_dqs = 0; + } + + // set dqs & dq by register read calibration result + cfg_dqs_rx(reg_dqs); + cfg_dq_rx(reg_dq); + CHECK_ERR_FLAG(mr_read_back,()); + uhs_phy_printf("reg_read_cal pass, latency= %d, dqs= %d, dq= %d\r\n",uhs_latency,reg_dqs,reg_dq); + break; + } + } + + return 0; +} + +void cfg_dq_drv(uint32_t dq){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); + // uhs_phy_delay_us(10); +} + +void cfg_dqs_drv(uint32_t dqs){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); + uhs_phy_delay_us(10); +} + +uint8_t reg_write_cal(void) //only need sweep dqs +{ + uint32_t tmpVal = 0; + // uint32_t tmpVal_1 = 0; + int32_t i = 0; + uint32_t reg_dqs; + uint32_t reg_dq = 0; + uint32_t reg_dqs1 = 0; + uint32_t reg_dqs2 = 0; + uint8_t dqs_dq_flag1 = 0; + uint8_t dqs_dq_flag2 = 0; + // reg_write_err = 0; + + // sweep1 dqs + for(i = 15; i >=0; i --) + { + cfg_dqs_drv(i); + CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,1)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1 + CHECK_ERR_FLAG(uhs_reg_r,(2,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + if(tmpVal == (16 + 32)) + { + uhs_phy_printf("reg write pass by -- dqs1= %d\r\n",i); + reg_dqs1 = i; + dqs_dq_flag1 = 1; + break; + } + else{ + uhs_phy_printf_debug("reg write fail by -- dqs1= %d\r\n",i); + } + } + // sweep2 dqs + for(i = 0; i <=15; i ++) + { + cfg_dqs_drv(i); + CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,2)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==0,BL_64==1 + CHECK_ERR_FLAG(uhs_reg_r,(2,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + if(tmpVal == (8 + 16)) + { + uhs_phy_printf("reg write pass by ++ dqs2= %d\r\n",i); + reg_dqs2 = i; + dqs_dq_flag2 = 1; + break; + } + else{ + uhs_phy_printf_debug("reg write fail by ++ dqs2= %d\r\n",i); + } + } + + if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 1){ + reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ; + }else if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 0){ + reg_dqs = reg_dqs1; + }else if(dqs_dq_flag1 == 0 && dqs_dq_flag2 == 1){ + reg_dqs = reg_dqs2; + } + else{ + reg_write_err = 1; + return uhs_err_handler(UHS_REG_WRITE_CAL_ERR); + } + + // if ck_dly_drv = 4, fix reg_dqs to 0 + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); + tmpVal = (tmpVal >> 16) & 0xF; + if(tmpVal == 4){ + reg_dqs = 0; + } + // set dqs by register write cal result + cfg_dqs_drv(reg_dqs); + CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,0)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1 + CHECK_ERR_FLAG(uhs_reg_r,(2,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + if(tmpVal == 0){ + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV); + uhs_phy_printf("reg write cal pass dqs= %d, dq= %d\r\n",reg_dqs,reg_dq); + } + else{ + reg_write_err = 2; + return uhs_err_handler(UHS_REG_WRITE_CAL_ERR); + } + + dqs_dq_delta = 16 + reg_dqs - reg_dq; + uhs_phy_printf("reg_write_cal return dqs_dq_delta= %d\r\n",dqs_dq_delta); + + return 0; +} + +void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) +{ + uint32_t addr_tmp = addr; + uint32_t data = data0; + uint32_t i = 0; + + if (print_flag){ + uhs_phy_printf("IN_ARRAY_WRITE_FIX\r\n"); + } + for(i = 0; i < (len>>2); i ++) + { + addr_tmp = (i << 2) + addr; + if((i % 2) == 0) + data = data0 + i; + else + data = data1 + i; + + BL_WR_WORD(addr_tmp,data); + } + if (print_flag){ + uhs_phy_printf("BEFORE CACHE FUCNTION\r\n"); + } + uhs_phy_delay_us(10); + if (print_flag){ + uhs_phy_printf("OUT_ARRAY_WRITE_FIX\r\n"); + } +} + +uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) +{ + uint8_t array_read_pass = 1; + uint32_t addr_tmp = addr; + uint32_t data = data0; + uint32_t data_read = 0; + uint32_t i = 0; + + if (print_flag){ + uhs_phy_printf("IN_ARRAY_READ_FIX\r\n"); + } + for(i = 0; i < (len>>2); i ++) + { + // data_read = 0; + // data_read += *((volatile uint8_t *)(addr+(i<<2)+3)); + // data_read <<= 8; + // data_read += *((volatile uint8_t *)(addr+(i<<2)+2)); + // data_read <<= 8; + // data_read += *((volatile uint8_t *)(addr+(i<<2)+1)); + // data_read <<= 8; + // data_read += *((volatile uint8_t *)(addr+(i<<2)+0)); + + addr_tmp = (i << 2) + addr; + data_read = BL_RD_WORD(addr_tmp); + if((i % 2) == 0) + data = data0 + i; + else + data = data1 + i; + + if (print_flag && i == 0){ + uhs_phy_printf("addr 0x%x, write_val 0x%x, read_val 0x%x\r\n",addr_tmp,data,data_read); + } + if(data_read != data){ + array_read_pass = 0; + uhs_phy_printf("addr 0x%x, write_val 0x%x, read_val error 0x%x\r\n",addr_tmp,data,data_read); + break; + } + } + if (print_flag){ + uhs_phy_printf("BEFORE CACHE FUCNTION\r\n"); + } + uhs_phy_delay_us(10); + if (print_flag){ + uhs_phy_printf("OUT_ARRAY_READ_FIX\r\n"); + } + return array_read_pass; +} + +void set_ck_dly_drv(uint32_t array_ck_dly_drv) +{ + uint32_t array_dqx_dly_drv = 0; + uint32_t array_dqsx_dly_drv = 0; + uint32_t array_cen_dly_drv = 0; + + uhs_phy_delay_us(10); // ck modify need time + + array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0; + array_cen_dly_drv = array_dqx_dly_drv + 1; + array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv; + array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv; + array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv; + + cfg_dq_drv(array_dqx_dly_drv); + // cfg_dqs_drv(array_dqsx_dly_drv); + cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv); + // uhs_phy_printf_debug("array_dqx_dly_drv= %d,array_dqsx_dly_drv= %d,array_ck_dly_drv= %d,array_cen_dly_drv= %d\r\n",array_dqx_dly_drv,array_dqsx_dly_drv,array_ck_dly_drv,array_cen_dly_drv); //debug + // uhs_phy_delay_us(50); // ck modify need time +} + +uint8_t array_read_latency_cal(void) +{ + // uint32_t tmpVal = 0; + uint32_t uhs_latency = 42; + // uint8_t array_ck_dly_drv_val[3] = {15,4,9}; + uint8_t array_ck_dly_drv_val[3] = {4,9,15}; + uint8_t ck_i; + uint32_t array_ck_dly_drv = 0; + int32_t i = 0; + uint32_t array_dqs = 0; + uint32_t array_dq = 0; + uint32_t dqs_flag; + uint32_t dq_flag; + uint32_t len = 128; + uint8_t rwindow = 0; + + for(uhs_latency = latency_wr[1]; uhs_latency > 0; uhs_latency --) + { + if(uhs_latency == 34) + { + array_read_err = 1; + return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR); + } + + uhs_phy_printf_debug("array read cal by latency= %d\r\n",uhs_latency); + set_uhs_latency_r(uhs_latency); + + for (ck_i = 0; ck_i < (sizeof(array_ck_dly_drv_val)/sizeof(array_ck_dly_drv_val[0])); ck_i++){ + array_ck_dly_drv = array_ck_dly_drv_val[ck_i]; + set_ck_dly_drv(array_ck_dly_drv); + uhs_phy_printf_debug("array read cal by ck= %d\r\n",array_ck_dly_drv); + + rwindow = 0; + + // sweep dqs + cfg_dq_rx(0); + for(i = 15; i >= 0; i --) + { + cfg_dqs_rx(i); + dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dqs_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by --dqs= %d\r\n",i); + array_dqs += i; + rwindow += i; + uhs_phy_cal_res->rwindow_end = i; + break; + } + } + for(i = 0; i <= 15; i ++) + { + cfg_dqs_rx(i); + dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dqs_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by ++dqs= %d\r\n",i); + array_dqs += i; + rwindow = (i > 0) ? (rwindow - i) : (rwindow + 1); + uhs_phy_cal_res->rwindow_begin = i; + break; + } + } + // sweep dq + cfg_dqs_rx(0); + for(i = 15; i >= 0; i --) + { + cfg_dq_rx(i); + dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dq_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by --dq= %d\r\n",i); + array_dq += i; + rwindow += i; + break; + } + } + for(i = 0; i <= 15; i ++) + { + cfg_dq_rx(i); + dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dq_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by ++dq= %d\r\n",i); + array_dq += i; + rwindow -= i; + break; + } + } + + if(dqs_flag == 1 || dq_flag == 1){ + if(array_dqs >= array_dq) + { + array_dqs = (array_dqs-array_dq)/2; + array_dq = 0; + } + else + { + #if CAL_MODE == 2 + array_read_err = 2; + return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR); + #endif + array_dq = (array_dq-array_dqs)/2; + array_dqs = 0; + } + cfg_dq_rx(array_dq); + cfg_dqs_rx(array_dqs); + uhs_phy_printf("array_read_dqs_dq_cal valid code number= %d\r\n",rwindow); + uhs_phy_cal_res->rwindow = rwindow; + uhs_phy_cal_res->rdqs = array_dqs; + uhs_phy_cal_res->rdq = array_dq; + uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %d, array_dq= %d\r\n",array_dqs,array_dq); + break; + } + } + if(dqs_flag == 1 || dq_flag == 1){ + uhs_phy_cal_res->rl = uhs_latency; + uhs_phy_printf("array_read_latency_cal pass, latency= %d, ck= %d\r\n",uhs_latency,array_ck_dly_drv); + break; + } + } + + return 0; +} + +uint8_t array_write_ck_cal(void) +{ + uint32_t array_ck_dly_drv = 0; + uint32_t array_ck_dly_drv1 = 15; + uint32_t array_ck_dly_drv2 = 4; + uint32_t flag_1 = 0; + uint32_t flag_2 = 0; + uint32_t len = 1024<<4; + + for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++) + { + set_ck_dly_drv(array_ck_dly_drv); + flag_2 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if (flag_2 == 0){ + uhs_phy_printf("array_write_ck_cal ck++ = %d, flag_2 = %d\r\n",array_ck_dly_drv,flag_2); + } + if(flag_2 == 0 && flag_ck2 == 0){ + flag_ck2 = 1; + uhs_phy_printf("array_write_ck_cal fail by ++ck= %d\r\n",array_ck_dly_drv); + array_ck_dly_drv2 = array_ck_dly_drv; + // break; + } + } + if (flag_ck2 == 1) + flag_2 = 0; + for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --) + { + set_ck_dly_drv(array_ck_dly_drv); + flag_1 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if (flag_1 == 0){ + uhs_phy_printf("array_write_ck_cal ck-- = %d, flag_1 = %d\r\n",array_ck_dly_drv,flag_1); + } + if(flag_1 == 0 && flag_ck1 == 0){ + flag_ck1 = 1; + uhs_phy_printf("array_write_ck_cal fail by --ck= %d\r\n",array_ck_dly_drv); + array_ck_dly_drv1 = array_ck_dly_drv; + // break; + } + } + if (flag_ck1 == 1) + flag_1 = 0; + + if (flag_1 == 0 && flag_2 == 0){ + if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4) + { + return uhs_err_handler(UHS_ARRAY_WRITE_CK_ERR); + } + else if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4)){ + array_ck_dly_drv = 15; + } + else{ + array_ck_dly_drv = 4; + } + } + else if (flag_1 == 0 && flag_2 == 1){ + array_ck_dly_drv = (array_ck_dly_drv1 > 9) ? 4 : 15; + }else if (flag_1 == 1 && flag_2 == 0){ + array_ck_dly_drv = (array_ck_dly_drv2 > 9) ? 4 : 15; + } + else { + array_ck_dly_drv = (15 + 4) / 2; + } + + set_ck_dly_drv(array_ck_dly_drv); + uhs_phy_cal_res->ck = array_ck_dly_drv; + uhs_phy_printf("array_write_ck_cal pass, ck= %d\r\n",array_ck_dly_drv); + + return 0; +} + +uint8_t array_read_dqs_dq_cal(void) +{ + int32_t i = 0; + uint32_t array_dqs = 0; + uint32_t array_dq = 0; + uint32_t dqs_flag; + uint32_t dq_flag; + uint32_t len = 128; + + // sweep dqs + cfg_dq_rx(0); + + for(i = 15; i >= 0; i --) + { + cfg_dqs_rx(i); + dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dqs_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by dqs= %d\r\n",i); + array_dqs = i; + break; + } + } + // sweep dq + cfg_dqs_rx(0); + for(i = 15; i >=0; i --) + { + cfg_dq_rx(i); + dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(dq_flag == 1) + { + uhs_phy_printf("array_read_dqs_dq_cal pass by dq= %d\r\n",i); + array_dq = i; + break; + } + } + if(dqs_flag == 0 && dq_flag == 0) + { + return uhs_err_handler(UHS_ARRAY_READ_CAL_ERR); + } + if(array_dqs > array_dq) + { + array_dqs = (array_dqs-array_dq)/2; + array_dq = 0; + } + else + { + array_dq = (array_dq-array_dqs)/2; + array_dqs = 0; + } + cfg_dq_rx(array_dq); + cfg_dqs_rx(array_dqs); + uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %d, array_dq= %d\r\n",array_dqs,array_dq); + + return 0; +} + +uint8_t array_write_dqs_dq_cal(void) +{ + uint32_t tmpVal = 0; + int32_t i = 0; + uint32_t dqs_flag1 = 0; + uint32_t dqs_flag2 = 0; + uint32_t array_dqs_dly_drv = 0; + uint32_t array_dqs_dly_drv1 = 0; + uint32_t array_dqs_dly_drv2 = 0; + + uint32_t addr = 0x50000000; + uint32_t len = 128; + uint32_t data0 = 0x23456789; + uint32_t data1 = 0x98765432; + + uint8_t wwindow = 0; + + for(i = 15; i >= 0; i --) + { + cfg_dqs_drv(i); + array_write_fix(addr,len,data0,data1); + dqs_flag1 = array_read_fix(addr,len,data0,data1); + if(dqs_flag1 == 1) + { + uhs_phy_printf("array_write_dqs_dq_cal pass by -- dqs1= %d\r\n",i); + array_dqs_dly_drv1 = i; + uhs_phy_cal_res->wwindow_end = i; + break; + } + else + { + uhs_phy_printf_debug("array_write_dqs_dq_cal fail by -- dqs1= %d\r\n",i); + } + } + for(i = 0; i <= 15; i ++) + { + cfg_dqs_drv(i); + array_write_fix(addr,len,data1,data0); + dqs_flag2 = array_read_fix(addr,len,data1,data0); + if(dqs_flag2 == 1) + { + uhs_phy_printf("array_write_dqs_dq_cal pass by ++ dqs2= %d\r\n",i); + array_dqs_dly_drv2 = i; + uhs_phy_cal_res->wwindow_begin = i; + break; + } + else + { + uhs_phy_printf_debug("array_write_dqs_dq_cal fail by ++ dqs2= %d\r\n",i); + } + } + + if(dqs_flag1 == 1 && dqs_flag2 == 1) + { + array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ; + } + else if(dqs_flag1 == 1 && dqs_flag2 == 0){ + array_dqs_dly_drv = array_dqs_dly_drv1; + }else if(dqs_flag1 == 0 && dqs_flag2 == 1){ + array_dqs_dly_drv = array_dqs_dly_drv2; + }else{ + return uhs_err_handler(UHS_ARRAY_WRITE_CAL_ERR); + } + + //debug + // array_dqs_dly_drv = 4; + + // if ck_dly_drv = 4, fix dqsx_dly_drv to 0 + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); + tmpVal = (tmpVal >> 16) & 0xF; + if(tmpVal == 4){ + array_dqs_dly_drv = 0; + uhs_phy_cal_res->wwindow_begin = 0; + } + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV); + + wwindow = (array_dqs_dly_drv > 0) ? (array_dqs_dly_drv1 - array_dqs_dly_drv2 + 1) : (array_dqs_dly_drv1 - 0 + 1); + uhs_phy_printf("array_write_dqs_dq_cal valid code number= %d\r\n",wwindow); + uhs_phy_cal_res->wwindow = wwindow; + uhs_phy_cal_res->wdqs = array_dqs_dly_drv; + uhs_phy_cal_res->wdq = tmpVal; + uhs_phy_printf("array_write_dqs_dq_cal pass by array_dqs_dly_drv= %d,array_dq_dly_drv= %d\r\n",array_dqs_dly_drv,tmpVal); + // set dqs by register write cal result + cfg_dqs_drv(array_dqs_dly_drv); + + return 0; +} + +BL_Err_Type GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq) +{ + uint32_t xtalFreq = 0; + uint32_t factor = 0; + GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = { + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + }; + GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = { + { NULL, 0x0 }, /*!< XTAL is None */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is 24M */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is 32M */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is 38.4M */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is 40M */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is 26M */ + { &uhsPllMCfg, 0x0 }, /*!< XTAL is RC32M */ + }; + GLB_PLL_REF_CLK_Type refClk; + + /* calc clkpllRefdivRatio */ + switch(xtalType){ + case GLB_XTAL_NONE: + return ERROR; + case GLB_XTAL_24M: + xtalFreq = 240; + uhsPllMCfg.clkpllRefdivRatio = 1; + break; + case GLB_XTAL_32M: + xtalFreq = 320; + uhsPllMCfg.clkpllRefdivRatio = 2; + break; + case GLB_XTAL_38P4M: + xtalFreq = 384; + uhsPllMCfg.clkpllRefdivRatio = 2; + break; + case GLB_XTAL_40M: + xtalFreq = 400; + uhsPllMCfg.clkpllRefdivRatio = 2; + break; + case GLB_XTAL_26M: + xtalFreq = 260; + uhsPllMCfg.clkpllRefdivRatio = 1; + break; + case GLB_XTAL_RC32M: + xtalFreq = 320; + uhsPllMCfg.clkpllRefdivRatio = 2; + break; + default : + break; + } + /* calc clkpllSelSampleClk */ + factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio); + if(factor<32*2048){ + uhsPllMCfg.clkpllSelSampleClk = 0; + }else if(factor<64*2048){ + uhsPllMCfg.clkpllSelSampleClk = 1; + }else if(factor<128*2048){ + uhsPllMCfg.clkpllSelSampleClk = 2; + }else{ + uhsPllMCfg.clkpllSelSampleClk = 2; + } + /* calc clkpllVcoSpeed */ + if(pllFreq<800){ + uhsPllMCfg.clkpllVcoSpeed = 1; + }else if(pllFreq<1000){ + uhsPllMCfg.clkpllVcoSpeed = 2; + }else if(pllFreq<1200){ + uhsPllMCfg.clkpllVcoSpeed = 3; + }else if(pllFreq<1500){ + uhsPllMCfg.clkpllVcoSpeed = 4; + }else if(pllFreq<1700){ + uhsPllMCfg.clkpllVcoSpeed = 5; + }else if(pllFreq<1900){ + uhsPllMCfg.clkpllVcoSpeed = 6; + }else if(pllFreq<2200){ + uhsPllMCfg.clkpllVcoSpeed = 7; + }else{ + uhsPllMCfg.clkpllVcoSpeed = 8; + } + /* calc clkpllEvenDivRatio */ + uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50; + /* calc clkpllSdmin */ + uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor; + uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor; + uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor; + uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor; + uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor; + uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor; + + if (xtalType == GLB_XTAL_RC32M) { + refClk = GLB_PLL_REFCLK_RC32M; + } else { + refClk = GLB_PLL_REFCLK_XTAL; + } + + // GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); + GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); + GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1); + + return SUCCESS; +} + +uint8_t init_reg_write(void){ + uint32_t tmpVal = 0; + uint8_t wl_i; + uint32_t wl; + uint32_t wdqs; + // uint8_t wdq_val[3] = {0,11,5}; + uint8_t wdq_val[3] = {0,5,11}; + uint8_t wdq_i; + uint32_t wdq; + uint32_t rl; + uint32_t rdqs; + uint32_t rdq; + uint8_t rl_i; + uint8_t wl_val_32[6] = {1,0,2,3,4,5}; + uint8_t rl_val_32[5] = {36,37,38,39,40}; + uint8_t wl_val_64[6] = {9,8,10,7,11,6}; + uint8_t rl_val_64[5] = {36,37,38,39,40}; + uint8_t wl_val[6]; + uint8_t rl_val[5]; + + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){ + wl_val[wl_i] = wl_val_32[wl_i]; + } + for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){ + rl_val[rl_i] = rl_val_32[rl_i]; + } + }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){ + wl_val[wl_i] = wl_val_64[wl_i]; + } + for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){ + rl_val[rl_i] = rl_val_64[rl_i]; + } + } + + // set to 2000Mbps + for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){ + rl = rl_val[rl_i]; + set_uhs_latency_r(rl); + for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){ + wl = wl_val[wl_i]; + latency_wr[0] = wl; + set_uhs_latency_w(wl); + for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){ + wdq = wdq_val[wdq_i]; + cfg_dq_drv(wdq); + cfg_ck_cen_drv(wdq + 4,wdq + 1); + for (wdqs = 0; wdqs <= 15; wdqs++){ + cfg_dqs_drv(wdqs); + set_uhs_phy_init(); + CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,0,0)); //uhs_latency_code==3,uhs_drive==2,ma==0,BL_32==0 + set_uhs_phy(); + rdq = 0; + cfg_dq_rx(rdq); + for (rdqs = 0; rdqs <= 15; rdqs++){ + cfg_dqs_rx(rdqs); + CHECK_ERR_FLAG(uhs_reg_r,(0,1)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%x, rdqs++\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)){ + uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + return 0; + } + else{ + uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + } + } + rdqs = 0; + cfg_dqs_rx(rdqs); + for (rdq = 0; rdq <= 15; rdq++){ + cfg_dq_rx(rdq); + CHECK_ERR_FLAG(uhs_reg_r,(0,1)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%x, rdq++\r\n",tmpVal); + if(tmpVal == ((2<<3)+uhs_latency_code)){ + uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + return 0; + } + else{ + uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + } + } + } + } + } + } + return uhs_err_handler(UHS_LATENCY_CODE_WRITE_ERR); +} + +uint8_t init_array_write(void){ + uint8_t wl_val[6] = {13,12,14,11,15,10}; + uint8_t wl_i; + uint32_t wl; + uint32_t wdqs; + // uint8_t wdq_val[3] = {0,11,5}; + uint8_t wdq_val[3] = {0,5,11}; + uint8_t wdq_i; + uint32_t wdq; + uint32_t rl; + uint32_t rdqs; + uint32_t rdq; + uint32_t len = 1024<<4; + uint32_t flag = 0; + print_flag = 1; + + for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){ + wl = wl_val[wl_i]; + latency_wr[0] = wl; + set_uhs_latency_w(wl); + for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){ + wdq = wdq_val[wdq_i]; + cfg_dq_drv(wdq); + cfg_ck_cen_drv(wdq + 4,wdq + 1); + for (wdqs = 0; wdqs <= 15; wdqs++){ + cfg_dqs_drv(wdqs); + array_write_fix(addr_rarray,len,data0_rarray,data1_rarray); + for (rl = latency_wr[1]; rl >= 35; rl--){ + set_uhs_latency_r(rl); + rdq = 0; + cfg_dq_rx(rdq); + for (rdqs = 0; rdqs <= 15; rdqs++){ + cfg_dqs_rx(rdqs); + flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(flag == 1){ + uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdqs++, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + print_flag = 0; + #if CAL_MODE == 2 + if(wl != 13){ + init_array_write_err = 2; + return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR); + } + #endif + uhs_phy_cal_res->wl = wl; + return 0; + } + else{ + uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdqs++, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + } + } + rdqs = 0; + cfg_dqs_rx(rdqs); + for (rdq = 0; rdq <= 15; rdq++){ + cfg_dq_rx(rdq); + flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray); + if(flag == 1){ + uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdq++, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + print_flag = 0; + #if CAL_MODE == 2 + if(wl != 13){ + init_array_write_err = 2; + return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR); + } + #endif + uhs_phy_cal_res->wl = wl; + return 0; + } + else{ + uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdq++, wl = %d, wdqs = %d, wdq = %d, rl = %d, rdqs = %d, rdq = %d\r\n",wl,wdqs,wdq,rl,rdqs,rdq); + } + } + } + } + } + } + init_array_write_err = 1; + return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR); +} + +void set_odt_en(void){ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MR2_2_0,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG,tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,0x2); //reg_mode_reg + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + uhs_phy_delay_us(10); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); + uhs_phy_delay_us(10); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); + + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0xf); // odt_sel + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_DLY,0x3); + BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal); +} + +uint8_t init_reg_write_2kM(void){ + uint32_t tmpVal = 0; + uint8_t wl_val[6] = {13,12,14,11,15,10}; + uint8_t wl_i; + uint32_t wl; + uint32_t wdqs; + // uint8_t wdq_val[3] = {0,11,5}; + uint8_t wdq_val[3] = {0,5,11}; + uint8_t wdq_i; + uint32_t wdq; + + // set to 2000Mbps + for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){ + wl = wl_val[wl_i]; + latency_wr[0] = wl; + set_uhs_latency_w(wl); + for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){ + wdq = wdq_val[wdq_i]; + cfg_dq_drv(wdq); + cfg_ck_cen_drv(wdq + 4,wdq + 1); + for (wdqs = 0; wdqs <= 15; wdqs++){ + cfg_dqs_drv(wdqs); + set_odt_en(); + CHECK_ERR_FLAG(uhs_reg_r,(2,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + uhs_phy_printf_debug("MA2 = 0x%x\r\n",tmpVal); + if(tmpVal == 3){ + uhs_phy_printf("2kM_REG_WRITE_SUCCESS, wl = %d, wdqs = %d, wdq = %d\r\n",wl,wdqs,wdq); + return 0; + } + else{ + uhs_phy_printf_debug("2kM_REG_WRITE_FAIL, wl = %d, wdqs = %d, wdq = %d\r\n",wl,wdqs,wdq); + } + } + } + } + return uhs_err_handler(UHS_REG_WRITE_2kM_ERR); +} + +uint8_t self_cal(void) +{ + uint32_t tmpVal = 0; + uint32_t datarate; + datarate = cfg_glb->pck_freq; + + if (datarate >= 933*2){ + uhs_latency_code = UHS_LATENCY_CODE_1066; + }else if(datarate >= 800*2){ + uhs_latency_code = UHS_LATENCY_CODE_933; + }else if(datarate >= 533*2){ + uhs_latency_code = UHS_LATENCY_CODE_800; + }else if(datarate >= 400*2){ + uhs_latency_code = UHS_LATENCY_CODE_533; + }else if(datarate >= 333*2){ + uhs_latency_code = UHS_LATENCY_CODE_400; + }else if(datarate >= 200*2){ + uhs_latency_code = UHS_LATENCY_CODE_333; + }else{ + uhs_latency_code = UHS_LATENCY_CODE_200; + } + // #if PSRAM_32MB + // PSRAM_UHS_Cfg_Type psramCfg = { + // datarate, + // PSRAM_MEM_SIZE_32MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + // #else + // PSRAM_UHS_Cfg_Type psramCfg = { + // datarate, + // PSRAM_MEM_SIZE_64MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + // #endif + + uhs_phy_printf("********** INIT_REG_WRITE **********\r\n"); + CHECK_ERR_FLAG(init_reg_write,()); //write latency code + // uhs_phy_printf("START_CAL_AT %dMbps\r\n",datarate); + // datarate_glb = datarate; + // ramsize_glb = cfg->psramMemSize; + GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate); + Psram_UHS_Init_Override(cfg_glb); //controller init + set_uhs_phy(); + + #if CAL_MODE == 0 + return 0; + // then load efuse, to set uhs phy regs + // call set_odt_en(), to set psram odt MR if need + // call mr_read_back() + #endif + + uhs_phy_printf("********** REG_READ_CAL **********\r\n"); + // uhs_phy_reg_dump(); + // ******register read latency & dqs & dq calibration + CHECK_ERR_FLAG(reg_read_cal,()); + if (cal_done_flag == 1) + return 0; + // if (datarate >= 1800){ + // latency_wr[1] = 39; + // }else if(datarate >= 1600){ + // latency_wr[1] = 38; + // }else if(datarate >= 1100){ + // latency_wr[1] = 37; + // }else{ + // latency_wr[1] = 36; + // } + + CHECK_ERR_FLAG(uhs_reg_r,(1,0)); + tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + tmpVal &= 0x10; + }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + tmpVal &= 0x20; + } + if (tmpVal != 0){ + return uhs_err_handler(UHS_BAD_DIE_ERR); + } + + uhs_phy_printf("UHS_PHY_CAL, ODT_EN = %d\r\n",ODT_EN); + #if ODT_EN + uhs_phy_printf("********** INIT_REG_WRITE_2kM **********\r\n"); + CHECK_ERR_FLAG(init_reg_write_2kM,()); + #endif + + uhs_phy_printf("********** INIT_ARRAY_WRITE **********\r\n"); + #if bl808_DBG_RF == 2 + uhs_phy_reg_dump(); + #endif + // reg_write_cal(); + CHECK_ERR_FLAG(init_array_write,()); + uhs_phy_printf("********** ARRAY_READ_CAL **********\r\n"); + // uhs_phy_reg_dump(); + // ******array read latency & dqs & dq calibration + CHECK_ERR_FLAG(array_read_latency_cal,()); + uhs_phy_printf("********** ARRAY_WRITE_CK_CAL **********\r\n"); + // uhs_phy_reg_dump(); + flag_ck1 = 0; + flag_ck2 = 0; + CHECK_ERR_FLAG(array_write_ck_cal,()); + uhs_phy_printf("********** ARRAY_WRITE_CAL **********\r\n"); + // uhs_phy_reg_dump(); + // array_read_dqs_dq_cal(); //calibrated in array_read_latency_cal + CHECK_ERR_FLAG(array_write_dqs_dq_cal,()); + // uhs_phy_reg_dump(); + + return 0; +} + +void soft_reset(void) +{ + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset + BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal); + uhs_phy_delay_ms(1); +} + +uint8_t uhs_diagonal_test(uint32_t data0,uint32_t data1) +{ + uint32_t RA = 0x0; //X_address + uint32_t CA = 0x0; //Y_address + uint32_t CA_init = 0x0; + uint32_t dataTmp; + uint32_t STRESS_TEST_BASE = 0x50000000; + uint32_t RowAddr = 0x3fff; //256Mb X_address + + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + RowAddr = 0x3fff; + }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + RowAddr = 0x7fff; + } + + // data0 + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + CA_init = (RA & 0x7f) << 3; + for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0; + } + } + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + CA_init = (RA & 0x7f) << 3; + for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE)); + if(dataTmp != data0){ + uhs_phy_printfe("addr: 0x%x\r\n", STRESS_TEST_BASE); + uhs_phy_printfe("data_w data0: 0x%x\r\n", data0); + uhs_phy_printfe("addr_r data0: 0x%x\r\n", dataTmp); + return uhs_err_handler(UHS_DIAGONAL_TEST_ERR); + } + } + } + // data1 + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + CA_init = (RA & 0x7f) << 3; + for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1; + } + } + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + CA_init = (RA & 0x7f) << 3; + for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE)); + if(dataTmp != data1){ + uhs_phy_printfe("addr: 0x%x\r\n", STRESS_TEST_BASE); + uhs_phy_printfe("data_w data1: 0x%x\r\n", data1); + uhs_phy_printfe("addr_r data1: 0x%x\r\n", dataTmp); + return uhs_err_handler(UHS_DIAGONAL_TEST_ERR); + } + } + } + + uhs_phy_printf("uhs_diagonal_test success\r\n"); + return 0; +} + +uint8_t uhs_all_addr_test(void) +{ + int32_t RA = 0x0; //X_address + int32_t CA = 0x0; //Y_address + uint32_t dataTmp; + uint32_t STRESS_TEST_BASE = 0x50000000; + uint32_t RowAddr = 0x3fff; //256Mb X_address + uint32_t data0 = 0xffffffff; + uint32_t data1 = 0x00000000; + + if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){ + RowAddr = 0x3fff; + }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){ + RowAddr = 0x7fff; + } + + // ****** Y_address -> X_address + //data0 + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0; + } + } + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for(CA = 0x0; CA <= 0x3ff; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE)); + if(dataTmp != data0){ + uhs_phy_printfe("addr: 0x%x\r\n", STRESS_TEST_BASE); + uhs_phy_printfe("data_w data0 first: 0x%x\r\n", data0); + uhs_phy_printfe("addr_r data0 first: 0x%x\r\n", dataTmp); + return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR); + } + } + } + // data1 + for (RA = 0x0; RA <= RowAddr; RA++){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1; + } + } + // ****** X_address -> Y_address + // data1 + for (RA = RowAddr; RA >= 0x0; RA--){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE)); + if(dataTmp != data1){ + uhs_phy_printfe("addr: 0x%x\r\n", STRESS_TEST_BASE); + uhs_phy_printfe("data_w data1: 0x%x\r\n", data1); + uhs_phy_printfe("addr_r data1: 0x%x\r\n", dataTmp); + return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR); + } + } + } + //data0 + for (RA = RowAddr; RA >= 0x0; RA--){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for (CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0; + } + } + for (RA = RowAddr; RA >= 0x0; RA--){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF; + STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0] + for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){ + STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800; + STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0; + dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE)); + if(dataTmp != data0){ + uhs_phy_printfe("addr: 0x%x\r\n", STRESS_TEST_BASE); + uhs_phy_printfe("data_w data0 second: 0x%x\r\n", data0); + uhs_phy_printfe("addr_r data0 second: 0x%x\r\n", dataTmp); + return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR); + } + } + } + uhs_phy_printf("uhs_all_addr_test success\r\n"); + return 0; +} + + +void dump_uhs_phy_cal_res(void) +{ + #if CAL_MODE != 2 + // dump uhs_phy_cal_res + uhs_phy_printf("uhs_phy_cal_res->cal_mode = %d\r\n",uhs_phy_cal_res->cal_mode); + uhs_phy_printf("uhs_phy_cal_res->err_type = %d\r\n",uhs_phy_cal_res->err_type); + uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %d\r\n",uhs_phy_cal_res->err_sub_type); + uhs_phy_printf("uhs_phy_cal_res->datarate = %d\r\n",uhs_phy_cal_res->datarate); + uhs_phy_printf("uhs_phy_cal_res->rl = %d\r\n",uhs_phy_cal_res->rl); + uhs_phy_printf("uhs_phy_cal_res->rdqs = %d\r\n",uhs_phy_cal_res->rdqs); + uhs_phy_printf("uhs_phy_cal_res->rdq = %d\r\n",uhs_phy_cal_res->rdq); + uhs_phy_printf("uhs_phy_cal_res->rwindow = %d\r\n",uhs_phy_cal_res->rwindow); + uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %d\r\n",uhs_phy_cal_res->rwindow_begin); + uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %d\r\n",uhs_phy_cal_res->rwindow_end); + uhs_phy_printf("uhs_phy_cal_res->ck = %d\r\n",uhs_phy_cal_res->ck); + uhs_phy_printf("uhs_phy_cal_res->wl = %d\r\n",uhs_phy_cal_res->wl); + uhs_phy_printf("uhs_phy_cal_res->wdqs = %d\r\n",uhs_phy_cal_res->wdqs); + uhs_phy_printf("uhs_phy_cal_res->wdq = %d\r\n",uhs_phy_cal_res->wdq); + uhs_phy_printf("uhs_phy_cal_res->wwindow = %d\r\n",uhs_phy_cal_res->wwindow); + uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %d\r\n",uhs_phy_cal_res->wwindow_begin); + uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %d\r\n",uhs_phy_cal_res->wwindow_end); + uhs_phy_printf("uhs_phy_cal_res->cal_done = %d\r\n",uhs_phy_cal_res->cal_done); + uhs_phy_printf("uhs_phy_cal_res->crc_res = %x\r\n",uhs_phy_cal_res->crc_res); + #else + // dump uhs_phy_cal_res + uhs_phy_printf("uhs_phy_cal_res->cal_mode = %d\r\n",uhs_phy_cal_res->cal_mode); + uhs_phy_printf("uhs_phy_cal_res->err_type = %x\r\n",uhs_phy_cal_res->err_type); + uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %d\r\n",uhs_phy_cal_res->err_sub_type); + uhs_phy_printf("uhs_phy_cal_res->datarate = %d\r\n",uhs_phy_cal_res->datarate); + uhs_phy_printf("uhs_phy_cal_res->rl = %d\r\n",uhs_phy_cal_res->rl); + uhs_phy_printf("uhs_phy_cal_res->rdqs = %d\r\n",uhs_phy_cal_res->rdqs); + uhs_phy_printf("uhs_phy_cal_res->rdq = %d\r\n",uhs_phy_cal_res->rdq); + uhs_phy_printf("uhs_phy_cal_res->rwindow = %d\r\n",uhs_phy_cal_res->rwindow); + uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %d\r\n",uhs_phy_cal_res->rwindow_begin); + uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %d\r\n",uhs_phy_cal_res->rwindow_end); + uhs_phy_printf("uhs_phy_cal_res->ck = %d\r\n",uhs_phy_cal_res->ck); + uhs_phy_printf("uhs_phy_cal_res->wl = %d\r\n",uhs_phy_cal_res->wl); + uhs_phy_printf("uhs_phy_cal_res->wdqs = %d\r\n",uhs_phy_cal_res->wdqs); + uhs_phy_printf("uhs_phy_cal_res->wdq = %d\r\n",uhs_phy_cal_res->wdq); + uhs_phy_printf("uhs_phy_cal_res->wwindow = %d\r\n",uhs_phy_cal_res->wwindow); + uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %d\r\n",uhs_phy_cal_res->wwindow_begin); + uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %d\r\n",uhs_phy_cal_res->wwindow_end); + uhs_phy_printf("uhs_phy_cal_res->cal_done = %x\r\n",uhs_phy_cal_res->cal_done); + uhs_phy_printf("uhs_phy_cal_res->crc_res = %x\r\n",uhs_phy_cal_res->crc_res); + #endif +} + +void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg) +{ + memset((void*)uhs_phy_cal_res, 0, sizeof(uhs_phy_cal_res_struct)); + uhs_phy_cal_res->cal_mode = CAL_MODE; + uhs_phy_cal_res->datarate = cfg->pck_freq; + + err_flag = 0; + + cfg_glb = cfg; + latency_wr_2kM[1] = 41; + uhs_phy_init_core(cfg); +} + +extern uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); +uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg) +{ + cal_done_flag = 0; + if(latency_wr_2kM[1] == 34) + { + reg_read_err = 3; + return uhs_err_handler(UHS_REG_READ_CAL_ERR); + } + + uint32_t pck_freq_temp; + + uhs_phy_printf_debug("uhs phy init\r\n"); + if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){ + uhs_phy_printf("\r\n########## START_CAL_AT %dMbps, PSRAM_MEM_SIZE_32MB, ##########\r\n",cfg->pck_freq); + }else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){ + uhs_phy_printf("\r\n########## START_CAL_AT %dMbps, PSRAM_MEM_SIZE_64MB, ##########\r\n",cfg->pck_freq); + } + #if CAL_MODE != 2 + uhs_phy_printf("CAL_MODE = %d\r\n",uhs_phy_cal_res->cal_mode); + #else + uhs_phy_printf("CAL_MODE = %d\r\n",uhs_phy_cal_res->cal_mode); + #endif + + power_up_mm(0); + power_up_uhspll(); + + power_up_ldo12uhs(); + set_cen_ck_ckn(); + + set_or_uhs(); + switch_to_ldo12uhs(); + release_cen_ck_ckn(); + + uint32_t tmpVal = 0; + tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en + BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal); + pck_freq_temp = cfg->pck_freq; + if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){ + cfg->pck_freq = 800; + // PSRAM_UHS_Cfg_Type psramCfg = { + // 800, + // PSRAM_MEM_SIZE_32MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + + GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,800); //stuck + Psram_UHS_Init_Override(cfg); // controller init + set_uhs_phy_init(); // phy init + set_uhs_latency_w(1); + set_uhs_latency_r(17); + psram_init(); // psram init after set freq & set_phy + + // uhs_reg_r(0,1); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + // uhs_phy_printf_debug("readout MA0 = 0x%x\r\n",tmpVal); + // if(tmpVal == ((2<<3)+5)) // 700M --> default uhs_latency_code == 5 + // { + // uhs_phy_printf_debug("register read pass at 700Mbps\r\n"); + // } + // else{ + // uhs_phy_printf_debug("register read fail at 700Mbps\r\n"); + // } + } + else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){ + cfg->pck_freq = 1400; + // PSRAM_UHS_Cfg_Type psramCfg = { + // 1400, + // PSRAM_MEM_SIZE_64MB, + // PSRAM_PAGE_SIZE_2KB, + // 0, + // }; + + GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400); //stuck + Psram_UHS_Init_Override(cfg); // controller init + set_uhs_phy_init(); // phy init + set_uhs_latency_w(9); + set_uhs_latency_r(30); + psram_init(); // psram init after set freq & set_phy + + // uhs_reg_r(0,1); + // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; + // if(tmpVal == ((2<<3)+1)) // 1400M --> default uhs_latency_code == 1 + // { + // uhs_phy_printf_debug("register read pass at 1400Mbps\r\n"); + // } + // else{ + // uhs_phy_printf_debug("register read fail at 1400Mbps\r\n"); + // } + } + + cfg->pck_freq = pck_freq_temp; + self_cal(); + uhs_phy_delay_ms(1); + cal_done_flag = 1; + #if CAL_MODE == 2 + if(err_flag == 0){ + uhs_phy_printf("********** UHS_DIAGONAL_TEST **********\r\n"); + uhs_diagonal_test(0x5555aaaa,0xaaaa5555); + // uhs_phy_printf("********** UHS_ALL_ADDR_TEST **********\r\n"); + // uhs_all_addr_test(); + } + // uhs_phy_printfe("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);l + uint32_t magic_os = 0x89abcdef; + uhs_phy_cal_res->err_type += magic_os; + uhs_phy_cal_res->cal_done = magic_os; + uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4); + #elif CAL_MODE == 1 + uhs_phy_cal_res->cal_done = 1; + uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4); + #endif + + #if CAL_MODE != 2 + uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type); + #else + uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %x !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type); + #endif + + dump_uhs_phy_cal_res(); + return uhs_phy_cal_res->err_type; +} diff --git a/drivers/ram/bflb/bl808_uhs_phy.h b/drivers/ram/bflb/bl808_uhs_phy.h new file mode 100644 index 00000000000..b5f1eea4fd4 --- /dev/null +++ b/drivers/ram/bflb/bl808_uhs_phy.h @@ -0,0 +1,117 @@ +#ifndef __UHS_PHY_H__ +#define __UHS_PHY_H__ + +#include "bl808_common.h" +#include "bl808_psram_uhs.h" +#include "bl808_glb.h" + +#ifndef CAL_MODE +#define CAL_MODE (0) // 0 is for sw call, 1 is for phy test, 2 is for ate cal +#endif + +enum { + UHS_LATENCY_CODE_533 = 3, // "0" + UHS_LATENCY_CODE_800 = 3, // "1" + UHS_LATENCY_CODE_933 = 3, // "2" + UHS_LATENCY_CODE_1066 = 3, + UHS_LATENCY_CODE_RESERVED = 3, //"4" + UHS_LATENCY_CODE_400 = 3, //"5" + UHS_LATENCY_CODE_333 = 3, //"6" + UHS_LATENCY_CODE_200 = 3, //"7" +}; + +enum{ + UHS_REGR_GNT_ERR = 1, + UHS_REGR_DONE_ERR, + UHS_REGW_GNT_ERR, + UHS_REGW_DONE_ERR, + UHS_LATENCY_CODE_WRITE_ERR, + UHS_INIT_ARRAY_WRITE_ERR, + UHS_REG_READ_CAL_ERR, + UHS_REG_WRITE_CAL_ERR, + UHS_ARRAY_READ_LAT_ERR, + UHS_ARRAY_WRITE_CK_ERR, + UHS_ARRAY_READ_CAL_ERR, + UHS_ARRAY_WRITE_CAL_ERR, + UHS_CACHE_ENABLE_ERR, + UHS_CACHE_DISABLE_ERR, + UHS_CACHE_RECOVER_ERR, + UHS_REG_WRITE_2kM_ERR, + UHS_BAD_DIE_ERR, + UHS_DIAGONAL_TEST_ERR, + UHS_ALL_ADDR_TEST_ERR, +}; + +#if CAL_MODE != 2 +typedef struct +{ + uint8_t rl :6; + uint8_t rdqs :4; + uint8_t rdq :4; + uint8_t wl :5; + uint8_t wdqs :4; + uint8_t wdq :4; + uint8_t ck :4; + uint8_t err_type; + uint8_t err_sub_type; + uint8_t cal_mode; + uint16_t datarate; + uint8_t rwindow; + uint8_t rwindow_begin; + uint8_t rwindow_end; + uint8_t wwindow; + uint8_t wwindow_begin; + uint8_t wwindow_end; + uint8_t cal_done; + uint32_t crc_res; +} uhs_phy_cal_res_struct; +#else +typedef struct +{ + uint32_t rl; + uint32_t rdqs; + uint32_t rdq; + uint32_t wl; + uint32_t wdqs; + uint32_t wdq; + uint32_t ck; + uint32_t err_type; + uint32_t err_sub_type; + uint32_t cal_mode; + uint32_t datarate; + uint32_t rwindow; + uint32_t rwindow_begin; + uint32_t rwindow_end; + uint32_t wwindow; + uint32_t wwindow_begin; + uint32_t wwindow_end; + uint32_t cal_done; + uint32_t crc_res; +} uhs_phy_cal_res_struct; +#endif +extern uhs_phy_cal_res_struct* uhs_phy_cal_res; + +// function call +void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg); +void uhs_phy_pwr_down(void); +uint8_t mr_read_back(void); +void set_odt_en(void); +// for htol test api +uint8_t uhs_all_addr_test(void); + +// for test or debug in example main.c +void soft_reset(void); +void uhs_reset(uint8_t ma_rb); +void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1); +uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1); +BL_Err_Type GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq); +// +void set_uhs_latency_r(uint32_t uhs_latency); +void set_uhs_latency_w(uint32_t uhs_latency); +void cfg_dq_drv(uint32_t dq); +void cfg_dqs_drv(uint32_t dqs); +void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv); +void cfg_dq_rx(uint8_t dq); +void cfg_dqs_rx(uint8_t dqs); + +#endif // __UHS_PHY_H__ diff --git a/drivers/ram/bflb/psram.c b/drivers/ram/bflb/psram.c new file mode 100644 index 00000000000..5860b561918 --- /dev/null +++ b/drivers/ram/bflb/psram.c @@ -0,0 +1,93 @@ +#include +#include + +#include "bl808_ef_cfg.h" +#include "bl808_psram_uhs.h" +#include "bl808_uhs_phy.h" + +#define WB_4MB_PSRAM (1) +#define UHS_32MB_PSRAM (2) +#define UHS_64MB_PSRAM (3) +#define WB_32MB_PSRAM (4) +#define NONE_UHS_PSRAM (-1) + +static PSRAM_UHS_Cfg_Type psramDefaultCfg = { + 2000, + PSRAM_MEM_SIZE_32MB, + PSRAM_PAGE_SIZE_2KB, + PSRAM_UHS_NORMAL_TEMP, +}; + +static int uhs_psram_init(void) +{ + Efuse_Chip_Info_Type chip_info; + EF_Ctrl_Get_Chip_Info(&chip_info); + if (chip_info.psramInfo == UHS_32MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB; + } else if (chip_info.psramInfo == UHS_64MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB; + } else { + return -1; + } + + Efuse_Psram_Trim_Type uhs_psram_trim; + EF_Ctrl_Read_Psram_Trim(&uhs_psram_trim); + + //init uhs PLL; Must open uhs pll first, and then initialize uhs psram + GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); + //init uhs psram ; + // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000); + Psram_UHS_x16_Init_Override(&psramDefaultCfg); + + // example: 2000Mbps typical cal values + uhs_phy_cal_res->rl = 39; + uhs_phy_cal_res->rdqs = 3; + uhs_phy_cal_res->rdq = 0; + uhs_phy_cal_res->wl = 13; + uhs_phy_cal_res->wdqs = 4; + uhs_phy_cal_res->wdq = 5; + uhs_phy_cal_res->ck = 9; + /* TODO: use uhs psram trim update */ + set_uhs_latency_r(uhs_phy_cal_res->rl); + cfg_dqs_rx(uhs_phy_cal_res->rdqs); + cfg_dq_rx(uhs_phy_cal_res->rdq); + set_uhs_latency_w(uhs_phy_cal_res->wl); + cfg_dq_drv(uhs_phy_cal_res->wdq); + cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1); + cfg_dqs_drv(uhs_phy_cal_res->wdqs); + // set_odt_en(); + mr_read_back(); + + return 0; +} + +static int bflb_psram_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = 0x50000000; + info->size = (psramDefaultCfg.psramMemSize + 1) * 1024 * 1024; + + return 0; +} + +static const struct ram_ops bflb_psram_ops = { + .get_info = bflb_psram_get_info, +}; + +static int bflb_psram_probe(struct udevice *dev) +{ + return uhs_psram_init(); +} + +static const struct udevice_id bflb_psram_ids[] = { + { .compatible = "bflb,bl808-psram-uhs" }, + { } +}; + +U_BOOT_DRIVER(bflb_psram) = { + .name = "bflb_psram", + .id = UCLASS_RAM, + .of_match = bflb_psram_ids, + .probe = bflb_psram_probe, + .ops = &bflb_psram_ops, + .flags = DM_FLAG_PRE_RELOC, +};