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riscv: Align the trap handler to 64 bytes

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This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Series-to: Rick Chen <rick@andestech.com>
Series-to: Leo <ycliang@andestech.com>
Series-cc: u-boot@lists.denx.de

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2023-02-19 13:22:09 -06:00
parent cbba1b7766
commit d38cb6f660
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/cpu/mtrap.S
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@ -26,7 +26,7 @@
.text
/* trap entry */
.align 2
.align 6
.global trap_entry
trap_entry:
addi sp, sp, -32 * REGBYTES