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rockchip: sdram: Ensure ram_base is correct in SPL

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Most Rockchip SoCs use 0x0 as DRAM base address, however some SoCs use
0x60000000 and RK3576 use 0x40000000 as DRAM base address.

CFG_SYS_SDRAM_BASE is defined with correct address for each SoC and
U-Boot proper use this to set correct gd->ram_base in setup_dest_addr().

SPL never assign any value to gd->ram_base and instead use the default,
0x0. Set correct gd->ram_base in dram_init() to ensure its correctness
in SPL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman 2025-01-30 22:07:13 +00:00 committed by Kever Yang
parent 356236126d
commit d5fc369a59
1 changed files with 1 additions and 0 deletions
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arch/arm/mach-rockchip/sdram.c
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@ -478,6 +478,7 @@ int dram_init(void)
debug("Cannot get DRAM size: %d\n", ret); debug("Cannot get DRAM size: %d\n", ret);
return ret; return ret;
} }
gd->ram_base = ram.base;
gd->ram_size = ram.size; gd->ram_size = ram.size;
debug("SDRAM base=%lx, size=%lx\n", debug("SDRAM base=%lx, size=%lx\n",
(unsigned long)ram.base, (unsigned long)ram.size); (unsigned long)ram.base, (unsigned long)ram.size);