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Merge tag 'u-boot-socfpga-next-20240415' of https://source.denx.de/u-boot/custodians/u-boot-socfpga

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- Add option to reprogram FPGA every reboot, enable this as default in
  chameleonv3 defconfig.
- Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG,
  so the driver can be built when CONFIG_SPL_SOCFPGA_DT_REG is set in
  defconfig.
This commit is contained in:
Tom Rini 2024-04-15 07:38:18 -06:00
commit d736d9f212
4 changed files with 16 additions and 3 deletions
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8
arch/arm/mach-socfpga/Kconfig
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@ -90,6 +90,14 @@ config TARGET_SOCFPGA_ARRIA10
imply FPGA_SOCFPGA imply FPGA_SOCFPGA
imply SPL_USE_TINY_PRINTF imply SPL_USE_TINY_PRINTF
config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
bool "Always reprogram Arria 10 FPGA"
depends on TARGET_SOCFPGA_ARRIA10
help
Arria 10 FPGA is only programmed during the cold boot.
This option forces the FPGA to be reprogrammed every reboot,
allowing to change the bitstream and apply it with warm reboot.
config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_CYCLONE5
bool bool
select TARGET_SOCFPGA_GEN5 select TARGET_SOCFPGA_GEN5

8
arch/arm/mach-socfpga/spl_a10.c
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@ -122,7 +122,10 @@ void spl_board_init(void)
arch_early_init_r(); arch_early_init_r();
/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
if (is_fpgamgr_user_mode()) { if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
is_regular_boot_valid()) ||
(!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
is_fpgamgr_user_mode())) {
ret = config_pins(gd->fdt_blob, "shared"); ret = config_pins(gd->fdt_blob, "shared");
if (ret) if (ret)
return; return;
@ -130,7 +133,8 @@ void spl_board_init(void)
ret = config_pins(gd->fdt_blob, "fpga"); ret = config_pins(gd->fdt_blob, "fpga");
if (ret) if (ret)
return; return;
} else if (!is_fpgamgr_early_user_mode()) { } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) ||
!is_fpgamgr_early_user_mode()) {
/* Program IOSSM(early IO release) or full FPGA */ /* Program IOSSM(early IO release) or full FPGA */
fpgamgr_program(buf, FPGA_BUFSIZ, 0); fpgamgr_program(buf, FPGA_BUFSIZ, 0);

1
configs/socfpga_chameleonv3_defconfig
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@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y
CONFIG_SPL_FS_FAT=y CONFIG_SPL_FS_FAT=y
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_SPL_FIT=y CONFIG_SPL_FIT=y

2
drivers/misc/Makefile
View File

@ -91,4 +91,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_K3) += k3_esm.o
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
obj-$(CONFIG_SL28CPLD) += sl28cpld.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o
obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o