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Convert CONFIG_BOARD_ECC_SUPPORT to Kconfig

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This converts the following to Kconfig:
   CONFIG_BOARD_ECC_SUPPORT

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-02-25 11:19:46 -05:00
parent 2c58d2fccf
commit da8592d5fa
3 changed files with 5 additions and 2 deletions
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5
arch/arm/mach-mvebu/Kconfig
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@ -152,6 +152,7 @@ config TARGET_OCTEONTX2_CN913x
config TARGET_DB_MV784MP_GP config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp" bool "Support db-mv784mp-gp"
select BOARD_ECC_SUPPORT
select MV78460 select MV78460
config TARGET_DS414 config TARGET_DS414
@ -160,6 +161,7 @@ config TARGET_DS414
config TARGET_MAXBCM config TARGET_MAXBCM
bool "Support maxbcm" bool "Support maxbcm"
select BOARD_ECC_SUPPORT
select MV78460 select MV78460
config TARGET_THEADORABLE config TARGET_THEADORABLE
@ -226,6 +228,9 @@ config DDR_RESET_ON_TRAINING_FAILURE
device will still hang - it doesn't make sense to reset the board device will still hang - it doesn't make sense to reset the board
in such a case. in such a case.
config BOARD_ECC_SUPPORT
bool
config SYS_BOARD config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG default "clearfog" if TARGET_CLEARFOG
default "helios4" if TARGET_HELIOS4 default "helios4" if TARGET_HELIOS4

1
include/configs/db-mv784mp-gp.h
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@ -72,6 +72,5 @@
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPD_EEPROM 0x4e #define CONFIG_SPD_EEPROM 0x4e
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */ #endif /* _CONFIG_DB_MV7846MP_GP_H */

1
include/configs/maxbcm.h
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@ -64,6 +64,5 @@
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_SDRAM_SIZE SZ_1G
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */ #endif /* _CONFIG_DB_MV7846MP_GP_H */