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Merge with /home/wd/git/u-boot/master

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This commit is contained in:
Wolfgang Denk 2005-08-12 00:22:49 +02:00
commit dafba16e6f
13 changed files with 460 additions and 785 deletions
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10
CHANGELOG
View File

@ -2,6 +2,16 @@
Changes for U-Boot 1.1.3: Changes for U-Boot 1.1.3:
====================================================================== ======================================================================
* Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 11 Aug 2005
* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
Patch by Stefan Roese, 11 Aug 2005
* Add NAND FLASH support for AMCC Bamboo 440EP eval board
Patch by Stefan Roese, 11 Aug 2005
* Add configuration for IFM AEV FIFO board. * Add configuration for IFM AEV FIFO board.
Minor coding style cleanup. Minor coding style cleanup.

6
Makefile
View File

@ -231,6 +231,9 @@ PATI_config: unconfig
## MPC5xxx Systems ## MPC5xxx Systems
######################################################################### #########################################################################
aev_config: unconfig
@./mkconfig -a aev ppc mpc5xxx tqm5200
hmi1001_config: unconfig hmi1001_config: unconfig
@./mkconfig hmi1001 ppc mpc5xxx hmi1001 @./mkconfig hmi1001 ppc mpc5xxx hmi1001
@ -359,9 +362,6 @@ spieval_config: unconfig
echo "... with automatic CS configuration" echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200 @./mkconfig -a spieval ppc mpc5xxx tqm5200
aev_config: unconfig
@./mkconfig -a aev ppc mpc5xxx tqm5200
######################################################################### #########################################################################
## MPC8xx Systems ## MPC8xx Systems
######################################################################### #########################################################################

122
board/amcc/bamboo/bamboo.c
View File

@ -29,6 +29,7 @@
void ext_bus_cntlr_init(void); void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void); void configure_ppc440ep_pins(void);
int is_nand_selected(void);
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0 #if 0
@ -132,10 +133,10 @@ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
EBC0_BNCR_BW_8BIT EBC0_BNCR_BW_8BIT
#define EBC0_BNCR_SMALL_FLASH_CS4 \ #define EBC0_BNCR_SMALL_FLASH_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87800000) | \ EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
EBC0_BNCR_BS_8MB | \ EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \ EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT EBC0_BNCR_BW_8BIT
/* Large Flash or SRAM */ /* Large Flash or SRAM */
#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
@ -273,6 +274,87 @@ int board_early_init_f(void)
return 0; return 0;
} }
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+
| nand_reset.
| Reset Nand flash
| This routine will abort previous cmd
+----------------------------------------------------------------------------*/
int nand_reset(ulong addr)
{
int wait=0, stat=0;
out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
while ((stat != 0xc0) && (wait != 0xffff)) {
stat = in8(addr + NAND_DATA_REG);
wait++;
}
if (stat == 0xc0) {
return 0;
} else {
printf("NAND Reset timeout.\n");
return -1;
}
}
void board_nand_set_device(int cs, ulong addr)
{
/* Set NandFlash Core Configuration Register */
out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
switch (cs) {
case 1:
/* -------
* NAND0
* -------
* K9F1208U0A : 4 addr cyc, 1 col + 3 Row
* Set NDF1CR - Enable External CS1 in NAND FLASH controller
*/
out32(addr + NAND_CR1_REG, 0x80002222);
break;
case 2:
/* -------
* NAND1
* -------
* K9K2G0B : 5 addr cyc, 2 col + 3 Row
* Set NDF2CR : Enable External CS2 in NAND FLASH controller
*/
out32(addr + NAND_CR2_REG, 0xC0007777);
break;
}
/* Perform Reset Command */
if (nand_reset(addr) != 0)
return;
}
void nand_init(void)
{
board_nand_set_device(1, CFG_NAND_ADDR);
nand_probe(CFG_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#if 0 /* NAND1 not supported yet */
board_nand_set_device(2, CFG_NAND2_ADDR);
nand_probe(CFG_NAND2_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
int checkboard(void) int checkboard(void)
{ {
sys_info_t sysinfo; sys_info_t sysinfo;
@ -585,7 +667,11 @@ int is_powerpc440ep_pass1(void)
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
int is_nand_selected(void) int is_nand_selected(void)
{ {
return FALSE; /* test-only */ #ifdef CONFIG_BAMBOO_NAND
return TRUE;
#else
return FALSE;
#endif
} }
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
@ -829,12 +915,8 @@ void ext_bus_cntlr_init(void)
/* NAND Flash */ /* NAND Flash */
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
/*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
ebc0_cs2_bnap_value = 0;
ebc0_cs2_bncr_value = 0;
ebc0_cs3_bnap_value = 0; ebc0_cs3_bnap_value = 0;
ebc0_cs3_bncr_value = 0; ebc0_cs3_bncr_value = 0;
} else { } else {
@ -985,7 +1067,7 @@ void ext_bus_cntlr_init(void)
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
uart_config_nb_t get_uart_configuration(void) uart_config_nb_t get_uart_configuration(void)
{ {
return (L4); /* test-only */ return (L4);
} }
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
@ -1132,8 +1214,7 @@ void ndfc_selection_in_fpga(void)
fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
} }
@ -1725,11 +1806,15 @@ void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t
*(core_select_P+UIC_0_3) = CORE_SELECTED; *(core_select_P+UIC_0_3) = CORE_SELECTED;
*(core_select_P+UIC_4_9) = CORE_SELECTED; *(core_select_P+UIC_4_9) = CORE_SELECTED;
*(core_select_P+SCP_CORE) = CORE_SELECTED; *(core_select_P+SCP_CORE) = CORE_SELECTED;
*(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
*(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
*(core_select_P+USB1_DEVICE) = CORE_SELECTED; *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
if (is_nand_selected()) {
*(core_select_P+NAND_FLASH) = CORE_SELECTED;
}
*config_val_P = CONFIG_IS_VALID; *config_val_P = CONFIG_IS_VALID;
} }
@ -1901,9 +1986,8 @@ void configure_ppc440ep_pins(void)
SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 ); SDR0_CUST0_CHIPSELGAT_EN1 |
/*SDR0_CUST0_CHIPSELGAT_EN2 ); */ SDR0_CUST0_CHIPSELGAT_EN2);
/*SDR0_CUST0_CHIPSELGAT_EN3 ); */
ndfc_selection_in_fpga(); ndfc_selection_in_fpga();
} }

11
board/amcc/bamboo/flash.c
View File

@ -50,15 +50,16 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* /*
* Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
*/ */
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
{0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
{0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
}; };
/* /*
@ -117,6 +118,10 @@ unsigned long flash_init(void)
index = 2; index = 2;
break; break;
} }
} else if (index == 0) {
if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
index = 8; /* sram below op code flash -> new index 8 */
}
} }
DEBUGF("\n"); DEBUGF("\n");

24
board/amcc/bamboo/init.S
View File

@ -86,14 +86,20 @@
tlbtab: tlbtab:
tlbtab_start tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the /*
dcache as stack. It is patched after relocation to enable SA_I * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
*/ * speed up boot process. It is patched after relocation to enable SA_I
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) */
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */ /* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
@ -102,6 +108,6 @@ tlbtab:
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */ /* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end tlbtab_end

1
board/amcc/yosemite/Makefile
View File

@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a LIB = lib$(BOARD).a
OBJS = $(BOARD).o OBJS = $(BOARD).o
OBJS += flash.o
SOBJS = init.o SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS) $(LIB): $(OBJS) $(SOBJS)

571
board/amcc/yosemite/flash.c
View File

@ -1,571 +0,0 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
/*
* Ported to XPedite1000, 1/2 mb boot flash only
* Travis B. Sawyer, <travis.sawyer@sandburst.com>
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
{0xfe000000}
};
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
#define ADDR0 0xaaaa
#define ADDR1 0x5554
#define FLASH_WORD_SIZE unsigned short
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
/* FLASH protect Monitor */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
return total_b;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_SST:
printf("SST ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A:
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s%s",
info->start[i],
erased ? " E" : " ", info->protect[i] ? "RO " : " ");
}
printf("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
udelay(10000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
debug("\ndev_code=%x\n", value);
#else
value = addr2[1]; /* device ID */
#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
info->flash_id = 0;
info->sector_count = CFG_MAX_FLASH_SECT;
info->size = 0x02000000;
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = (int)base + (i * 0x00020000);
info->protect[i] = 0;
}
*(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
return (info->size);
}
int wait_for_DQ7(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr =
(FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
printf("Erasing sector %p\n", addr2);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x0080;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
asm("sync");
asm("isync");
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
ulong status_value = 0;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
/*print status if needed */
if ((wp >= (status_value + 0x20000))
&& (status_value < 0xFFFE0000)) {
status_value = wp;
printf("writing to sector 0x%X\n", status_value);
}
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr2 = (vu_long *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00A0;
asm("sync");
asm("isync");
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

21
board/amcc/yosemite/init.S
View File

@ -86,14 +86,19 @@
tlbtab: tlbtab:
tlbtab_start tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the /*
dcache as stack. It is patched after relocation to enable SA_I * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
*/ * speed up boot process. It is patched after relocation to enable SA_I
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) */
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */ /* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )

55
board/amcc/yosemite/yosemite.c
View File

@ -20,9 +20,12 @@
*/ */
#include <common.h> #include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <spd_sdram.h> #include <spd_sdram.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
int board_early_init_f(void) int board_early_init_f(void)
{ {
register uint reg; register uint reg;
@ -35,7 +38,7 @@ int board_early_init_f(void)
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */ mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000); mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000); mtebc(pb1cr, 0x00000000);
@ -122,6 +125,54 @@ int board_early_init_f(void)
return 0; return 0;
} }
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint pbcr;
int size_val = 0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
return 0;
}
int checkboard(void) int checkboard(void)
{ {
sys_info_t sysinfo; sys_info_t sysinfo;
@ -135,6 +186,8 @@ int checkboard(void)
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000); printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0); return (0);
} }

8
cpu/ppc4xx/440gx_enet.c
View File

@ -375,8 +375,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3)))); (RGMII_FER_RGMII << RGMII_FER_V (3))));
} }
#endif #endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
__asm__ volatile ("eieio"); __asm__ volatile ("eieio");
@ -521,13 +521,13 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
} }
mtsdr(sdr_mfr, reg); mtsdr(sdr_mfr, reg);
#endif #endif
/* Set ZMII/RGMII speed according to the phy link speed */ /* Set ZMII/RGMII speed according to the phy link speed */
reg = in32 (ZMII_SSR); reg = in32 (ZMII_SSR);
if ( (speed == 100) || (speed == 1000) ) if ( (speed == 100) || (speed == 1000) )
out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
else else
out32 (ZMII_SSR, out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) { if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000) if (speed == 1000)
@ -672,7 +672,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */ /* set RX buffer size */
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break; break;
#endif /*CONFIG_440GX */ #endif /* CONFIG_440GX */
case 0: case 0:
default: default:
/* setup MAL tx & rx channel pointers */ /* setup MAL tx & rx channel pointers */

138
include/configs/bamboo.h
View File

@ -32,11 +32,18 @@
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
* Please note that, if NAND support is enabled, the 2nd ethernet port
* can't be used because of pin multiplexing. So, if you want to use the
* 2nd ethernet port you have to "undef" the following define.
*/
#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the * Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses) * actual resources get mapped (not physical addresses)
@ -58,13 +65,15 @@
#define CFG_USB_DEVICE 0x50000000 #define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000 #define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) #define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_NAND_ADDR 0x90000000
#define CFG_NAND2_ADDR 0x94000000
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM) * Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END 0x1000 #define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@ -88,7 +97,7 @@
* The DS1558 code assumes this condition * The DS1558 code assumes this condition
* *
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -118,21 +127,80 @@
#define CFG_FLASH_ADDR1 0x2aa #define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char #define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ #define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ #define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH #ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#if 0 /* test-only */
/* Address and size of Redundant Environment Sector */ /* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#endif /* CFG_ENV_IS_IN_FLASH */ #endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NAND-FLASH related
*----------------------------------------------------------------------*/
#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
#define NAND0_CMD_READ2 0x50
#define NAND0_CMD_READ_ID 0x90
#define NAND0_CMD_READ_STATUS 0x70
#define NAND0_CMD_RESET 0xFF
#define NAND0_CMD_PAGE_PROG 0x80
#define NAND0_CMD_PAGE_PROG_TRUE 0x10
#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
#define NAND0_CMD_BLOCK_ERASE 0x60
#define NAND0_CMD_BLOCK_ERASE_END 0xD0
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
/* not needed with 440EP NAND controller */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* DDR SDRAM * DDR SDRAM
*----------------------------------------------------------------------------- */ *----------------------------------------------------------------------------- */
@ -206,10 +274,14 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#ifndef CONFIG_BAMBOO_NAND
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 1 #define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#endif /* CONFIG_BAMBOO_NAND */
#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */ #define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
@ -228,8 +300,15 @@
#define USB_2_0_DEVICE #define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/ #endif /*CONFIG_440EP*/
#ifdef CONFIG_BAMBOO_NAND
#define _CFG_CMD_NAND CFG_CMD_NAND
#else
#define _CFG_CMD_NAND 0
#endif /* CONFIG_BAMBOO_NAND */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \ CFG_CMD_ASKENV | \
CFG_CMD_EEPROM | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
@ -244,6 +323,7 @@
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_USB | \ CFG_CMD_USB | \
_CFG_CMD_NAND | \
CFG_CMD_SNTP ) CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@ -253,42 +333,42 @@
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* PCI stuff * PCI stuff
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
/* General PCI */ /* General PCI */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */ /* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT #define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT #define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data
@ -300,7 +380,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ #define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */ #define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */

6
include/configs/bubinga.h
View File

@ -127,6 +127,10 @@
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
@ -199,8 +203,6 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C stuff * I2C stuff
*----------------------------------------------------------------------- *-----------------------------------------------------------------------

272
include/configs/yosemite.h
View File

@ -1,4 +1,6 @@
/* /*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -28,56 +30,53 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* High Level Configuration Options * High Level Configuration Options
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */ #define CONFIG_YOSEMITE 1 /* Board is Yosemite */
#define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the * Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses) * actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/ /*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/ /*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000 #define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000 #define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR 0xf0000000
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM) * Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000 #define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Serial Port * Serial Port
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 9600 #define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1 #define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/ /*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE #undef CONFIG_UART1_CONSOLE
@ -85,26 +84,21 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* NVRAM/RTC * Environment
*
* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ /*
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ * Define here the location of the environment variables (FLASH or EEPROM).
* Note: DENX encourages to use redundant environment in FLASH.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#endif
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH related * FLASH related
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#if 1 /* test-only */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
@ -116,12 +110,24 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#endif
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* DDR SDRAM * DDR SDRAM
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C * I2C
@ -131,44 +137,70 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1) #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ #ifdef CFG_ENV_IS_IN_EEPROM
#define CONFIG_BOOTDELAY 3 /* disable autoboot */ #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=yosemite\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3 #define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.4.251
#define CONFIG_ETHADDR 00:10:EC:00:12:34
#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.0.4.115
/* Partitions */ /* Partitions */
#define CONFIG_MAC_PARTITION #define CONFIG_MAC_PARTITION
@ -190,53 +222,21 @@
#define CONFIG_HW_WATCHDOG /* watchdog */ #define CONFIG_HW_WATCHDOG /* watchdog */
#endif #endif
#ifdef CONFIG_440EP #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
/* Need to define POST */ CFG_CMD_ASKENV | \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \
CFG_CMD_DATE | \ CFG_CMD_DIAG | \
CFG_CMD_DHCP | \ CFG_CMD_ELF | \
CFG_CMD_DIAG | \ CFG_CMD_I2C | \
CFG_CMD_ECHO | \ CFG_CMD_IRQ | \
CFG_CMD_EEPROM | \ CFG_CMD_MII | \
CFG_CMD_ELF | \ CFG_CMD_NET | \
/* CFG_CMD_EXT2 |*/ \ CFG_CMD_NFS | \
/* CFG_CMD_FAT |*/ \ CFG_CMD_PCI | \
CFG_CMD_I2C | \ CFG_CMD_PING | \
/* CFG_CMD_IDE |*/ \ CFG_CMD_REGINFO | \
CFG_CMD_IRQ | \ CFG_CMD_SDRAM | \
/* CFG_CMD_KGDB |*/ \ CFG_CMD_USB )
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS)
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
@ -245,42 +245,42 @@
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* PCI stuff * PCI stuff
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
/* General PCI */ /* General PCI */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */ /* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT #define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT #define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data
@ -288,10 +288,11 @@
* the maximum mapped by the Linux kernel during initialization. * the maximum mapped by the Linux kernel during initialization.
*/ */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ #define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */ #define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
@ -309,4 +310,5 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif #endif
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */