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imx: imx8m: clock: not configure reserved SRC register

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i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Peng Fan 2023-06-15 18:09:21 +08:00 committed by Stefano Babic
parent e8cd1f60d9
commit dc2d49209e
1 changed files with 0 additions and 1 deletions
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arch/arm/mach-imx/imx8m/clock_imx8mm.c
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@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
case ANATOP_DRAM_PLL:
setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
pll_base = &ana_pll->dram_pll_gnrl_ctl;
break;