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spi: synquacer: DMSTART bit must not be set while transferring

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DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Masahisa Kojima 2022-05-17 17:41:38 +09:00 committed by Tom Rini
parent 88d50ed8a1
commit de9f2c9c2e
1 changed files with 5 additions and 3 deletions
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8
drivers/spi/spi-synquacer.c
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@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
writel(~0, priv->base + RXC); writel(~0, priv->base + RXC);
/* Trigger */ /* Trigger */
val = readl(priv->base + DMSTART); if (flags & SPI_XFER_BEGIN) {
val |= BIT(TRIGGER); val = readl(priv->base + DMSTART);
writel(val, priv->base + DMSTART); val |= BIT(TRIGGER);
writel(val, priv->base + DMSTART);
}
while (busy & (BIT(RXBIT) | BIT(TXBIT))) { while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
if (priv->rx_words) if (priv->rx_words)