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Merge tag 'fsl-qoriq-2022-7-3' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

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Several patches from Pali
 - fsl_elbc detection fix
 - sort p2020 dts node, drop duplicated node
 - p1_p2_rdb_pc board cleanup
 - simplify mpc85xx _start_cont jumping code
This commit is contained in:
Tom Rini 2022-07-04 21:30:23 -04:00
commit e1d3e637c7
8 changed files with 49 additions and 67 deletions
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5
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -1126,9 +1126,8 @@ switch_as:
#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
addi r3,r3,_start_cont - CONFIG_VAL(SYS_MONITOR_BASE)
lis r3,_start_cont@h
ori r3,r3,_start_cont@l
mtlr r3
blr
#endif

77
arch/powerpc/dts/p2020-post.dtsi
View File

@ -13,49 +13,6 @@
compatible = "fsl,p2020-immr", "simple-bus";
bus-frequency = <0x0>;
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
reg = <0x22000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <28 0x2 0 0>;
phy_type = "ulpi";
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
esdhc: sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2 0 0>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
interrupts = < 0x3b 0x02 0x00 0x00 >;
fsl,espi-num-chipselects = <4>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-gpio-0.dtsi"
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
@ -74,6 +31,22 @@
interrupts = <18 2 0 0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
interrupts = < 0x3b 0x02 0x00 0x00 >;
fsl,espi-num-chipselects = <4>;
};
/include/ "pq3-dma-1.dtsi"
/include/ "pq3-gpio-0.dtsi"
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
@ -83,7 +56,15 @@
};
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-dma-1.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
reg = <0x22000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <28 0x2 0 0>;
phy_type = "ulpi";
};
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-timer-0.dtsi"
@ -95,6 +76,14 @@
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
esdhc: sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2 0 0>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
/include/ "pq3-sec3.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"

1
board/freescale/p1_p2_rdb_pc/law.c
View File

@ -9,7 +9,6 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif

11
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -186,7 +186,11 @@ int checkboard(void)
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
/* FIXME: This should just use the model from the device tree or similar */
printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", BOARD_NAME,
#ifdef BOARD_NAME
printf("Board: %s ", BOARD_NAME);
#endif
printf("CPLD: V%d.%d PCBA: V%d.0\n",
in_8(&cpld_data->cpld_rev_major) & 0x0F,
in_8(&cpld_data->cpld_rev_minor) & 0x0F,
in_8(&cpld_data->pcba_rev) & 0x0F);
@ -224,8 +228,11 @@ int checkboard(void)
val = (in & io_config) | (out & (~io_config));
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
if (0) {
#ifdef __SW_BOOT_SD
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
#endif
#ifdef __SW_BOOT_SD2
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
puts("sd");

3
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE

6
drivers/mtd/nand/raw/fsl_elbc_nand.c
View File

@ -745,7 +745,11 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev)
return ret;
/* If nand_scan_ident() has not selected ecc.mode, do it now */
if (nand->ecc.mode == NAND_ECC_NONE) {
if (nand->ecc.mode == 0
#if CONFIG_IS_ENABLED(OF_CONTROL)
&& !ofnode_read_string(nand->flash_node, "nand-ecc-mode")
#endif
) {
/* If CS Base Register selects full hardware ECC then use it */
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
nand->ecc.mode = NAND_ECC_HW;

9
include/configs/p1_p2_rdb_pc.h
View File

@ -173,7 +173,6 @@
* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
* (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
@ -280,14 +279,6 @@
#endif
/* CPLD config size: 1Mb */
#define CONFIG_SYS_PMC_BASE 0xff980000
#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
BR_PS_8 | BR_V)
#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"

4
scripts/config_whitelist.txt
View File

@ -418,8 +418,6 @@ CONFIG_PHY_IRAM_BASE
CONFIG_PL011_CLOCK
CONFIG_PL01x_PORTS
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
CONFIG_PME_PLAT_CLK_DIV
CONFIG_POST
CONFIG_POSTBOOTMENU
@ -1413,8 +1411,6 @@ CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_SETTLING_TIME
CONFIG_SYS_PMAN
CONFIG_SYS_PMC_BASE
CONFIG_SYS_PMC_BASE_PHYS
CONFIG_SYS_PME_CLK
CONFIG_SYS_POST_MEMORY
CONFIG_SYS_POST_MEM_REGIONS