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sunxi: board: Fix UART PortF pinmux setup

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When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins
(usually used for the SD card) as UART0. Some SoCs use the mux value of
3 for this, while others use 4.

The combination of Kconfig symbols we currently use was not quite right:
we mis-configure the A31, A64, H6 and H616.

Going through the list in the pinctrl driver, there are only a few older
SoCs that use a value of 4, so revert the #ifdef clause, and name those
explicitly, instead of the other way around.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Andre Przywara 2022-05-06 00:34:39 +01:00
parent d6cb09d89d
commit e26ece267e
1 changed files with 7 additions and 6 deletions
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13
arch/arm/mach-sunxi/board.c
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@ -87,15 +87,16 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif #endif
#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \ #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
defined(CONFIG_MACH_SUNIV) defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#else
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#endif #endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1); sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);