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https://github.com/smaeul/u-boot.git
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arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree
Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very similar and hence can share the same device tree for boot loaders purpose. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Stefan Agner
Stefano Babic
parent
bdad02e1e2
commit
e60f74907d
@ -283,6 +283,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb
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dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
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k2l-evm.dtb \
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k2e-evm.dtb \
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92
arch/arm/dts/imx7-colibri.dts
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92
arch/arm/dts/imx7-colibri.dts
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@ -0,0 +1,92 @@
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/*
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* Copyright 2016 Toradex AG
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx7.dtsi"
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/ {
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model = "Toradex Colibri iMX7S/D";
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compatible = "toradex,imx7-colibri", "fsl,imx7";
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chosen {
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stdout-path = &uart1;
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};
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-1 = <&pinctrl_i2c4_gpio>;
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sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
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scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
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uart-has-rtscts;
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fsl,dte-mode;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c4: i2c4-grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
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MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4_gpio: i2c4-gpio-grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
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MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
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>;
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};
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pinctrl_uart1: uart1-grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
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MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
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MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
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MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
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>;
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};
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pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
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fsl,pins = <
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MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
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MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_i2c1: i2c1-grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
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MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c1_gpio: i2c1-gpio-grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
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MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
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>;
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};
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};
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194
arch/arm/dts/imx7.dtsi
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194
arch/arm/dts/imx7.dtsi
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@ -0,0 +1,194 @@
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/*
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* Copyright 2016 Toradex AG
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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#include "imx7d-pinfunc.h"
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#include "skeleton.dtsi"
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/ {
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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aips1: aips-bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000000 0x400000>;
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ranges;
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gpio1: gpio@30200000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30200000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@30210000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30210000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@30220000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30220000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio4: gpio@30230000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30230000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio5: gpio@30240000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30240000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio6: gpio@30250000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30250000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio7: gpio@30260000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30260000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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iomuxc_lpsr: iomuxc-lpsr@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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};
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};
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aips3: aips-bus@30800000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30800000 0x400000>;
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ranges;
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uart1: serial@30860000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30860000 0x10000>;
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status = "disabled";
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};
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uart2: serial@30890000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30890000 0x10000>;
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status = "disabled";
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};
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uart3: serial@30880000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30880000 0x10000>;
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status = "disabled";
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};
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i2c1: i2c@30a20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
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reg = <0x30a20000 0x10000>;
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status = "disabled";
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};
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i2c2: i2c@30a30000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
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reg = <0x30a30000 0x10000>;
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status = "disabled";
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};
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i2c3: i2c@30a40000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
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reg = <0x30a40000 0x10000>;
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status = "disabled";
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};
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i2c4: i2c@30a50000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
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reg = <0x30a50000 0x10000>;
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status = "disabled";
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};
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uart4: serial@30a60000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30a60000 0x10000>;
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status = "disabled";
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};
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uart5: serial@30a70000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30a70000 0x10000>;
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status = "disabled";
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};
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uart6: serial@30a80000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30a80000 0x10000>;
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status = "disabled";
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};
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uart7: serial@30a90000 {
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compatible = "fsl,imx7d-uart",
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"fsl,imx6q-uart";
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reg = <0x30a90000 0x10000>;
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status = "disabled";
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};
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};
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};
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};
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