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configs: Re-run migrations

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As the CI test for stopping platforms from being merged that were
defining symbols that had Kconfig entries, a small number of symbols
needed to be migrated again.  Do so, and catch two cases the README
should also have been updated but was not.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-03-11 07:12:48 -05:00
parent ab366418b5
commit eb8eb31749
14 changed files with 15 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
README
View File

@ -565,13 +565,6 @@ The following options need to be configured:
boards with QUICC Engines require OF_QE to set UCC MAC boards with QUICC Engines require OF_QE to set UCC MAC
addresses addresses
CONFIG_OF_SYSTEM_SETUP
Other code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel.
This causes ft_system_setup() to be called before booting
the kernel.
CONFIG_OF_IDE_FIXUP CONFIG_OF_IDE_FIXUP
U-Boot can detect if an IDE device is present or not. U-Boot can detect if an IDE device is present or not.
@ -1847,10 +1840,6 @@ The following options need to be configured:
CONFIG_SPL_SKIP_RELOCATE CONFIG_SPL_SKIP_RELOCATE
Avoid SPL relocation Avoid SPL relocation
CONFIG_SPL_NAND_IDENT
SPL uses the chip ID list to identify the NAND flash.
Requires CONFIG_SPL_NAND_BASE.
CONFIG_SPL_UBI CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and Support for a lightweight UBI (fastmap) scanner and
loader loader

2
configs/imx8mn_var_som_defconfig
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@ -31,6 +31,8 @@ CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y CONFIG_SPL_WATCHDOG=y

3
configs/imx8mp_rsb3720a1_4G_defconfig
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@ -22,9 +22,12 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1" CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE=y

3
configs/imx8mp_rsb3720a1_6G_defconfig
View File

@ -22,9 +22,12 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1" CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE=y

1
configs/j721s2_evm_a72_defconfig
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@ -135,6 +135,7 @@ CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET=y

1
configs/j721s2_evm_r5_defconfig
View File

@ -111,6 +111,7 @@ CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET=y

4
configs/kontron_pitx_imx8m_defconfig
View File

@ -20,14 +20,18 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set # CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y CONFIG_SPL_WATCHDOG=y

1
configs/verdin-imx8mp_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x43500000 CONFIG_SYS_LOAD_ADDR=0x43500000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_EXTERNAL_OFFSET=0x3000

5
include/configs/imx8mn_var_som.h
View File

@ -14,8 +14,6 @@
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \ #define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
@ -84,7 +82,4 @@
/* USDHC */ /* USDHC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* I2C */
#define CONFIG_SYS_I2C_SPEED 400000
#endif /* __IMX8MN_VAR_SOM_H */ #endif /* __IMX8MN_VAR_SOM_H */

25
include/configs/imx8mp_rsb3720.h
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@ -18,11 +18,9 @@
#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000 #define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 #define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ #define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
@ -37,26 +35,11 @@
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#if defined(CONFIG_NAND_BOOT) #if defined(CONFIG_NAND_BOOT)
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DMA
#define CONFIG_SPL_NAND_MXS #define CONFIG_SPL_NAND_MXS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_IDENT
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of \
* first 64MB boot area \
*/
/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
* boot image (not only FIT part) to the mtdpart, so we check both two offsets
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
#endif #endif
#endif #endif
#define CONFIG_REMAKE_ELF
/* ENET Config */ /* ENET Config */
/* ENET1 */ /* ENET1 */
#if defined(CONFIG_CMD_NET) #if defined(CONFIG_CMD_NET)
@ -186,15 +169,12 @@
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
/* Monitor Command Prompt */ /* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16) sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_IMX_BOOTAUX
#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
@ -213,11 +193,6 @@
/* NAND stuff */ /* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000 #define CONFIG_SYS_NAND_BASE 0x20000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif /* CONFIG_NAND_MXS */ #endif /* CONFIG_NAND_MXS */
#define CONFIG_SYS_I2C_SPEED 100000
#endif /* __IMX8MP_RSB3720_H */ #endif /* __IMX8MP_RSB3720_H */

3
include/configs/j721s2_evm.h
View File

@ -60,9 +60,6 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_CQSPI_REF_CLK 133333333 #define CONFIG_CQSPI_REF_CLK 133333333
/* HyperFlash related configuration */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
/* U-Boot general configuration */ /* U-Boot general configuration */
#define EXTRA_ENV_J721S2_BOARD_SETTINGS \ #define EXTRA_ENV_J721S2_BOARD_SETTINGS \
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \

7
include/configs/kontron_pitx_imx8m.h
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@ -11,11 +11,8 @@
#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K) #define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0 #define CONFIG_SPL_STACK 0x187FF0
#define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
@ -33,8 +30,6 @@
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif #endif
#define CONFIG_REMAKE_ELF
/* ENET1 Config */ /* ENET1 Config */
#if defined(CONFIG_CMD_NET) #if defined(CONFIG_CMD_NET)
#define CONFIG_ETHPRIME "FEC" #define CONFIG_ETHPRIME "FEC"
@ -92,6 +87,4 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_OF_SYSTEM_SETUP
#endif #endif

1
include/configs/ten64.h
View File

@ -9,7 +9,6 @@
#include "ls1088a_common.h" #include "ls1088a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1

4
include/configs/verdin-imx8mp.h
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@ -16,7 +16,6 @@
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000 #define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00 #define CONFIG_SPL_BSS_START_ADDR 0x0098fc00
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K #define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
@ -31,11 +30,8 @@
#define CONFIG_POWER_PCA9450 #define CONFIG_POWER_PCA9450
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#endif /* CONFIG_SPL_BUILD */ #endif /* CONFIG_SPL_BUILD */
#define CONFIG_REMAKE_ELF
/* ENET Config */ /* ENET Config */
/* ENET1 */ /* ENET1 */
#if defined(CONFIG_CMD_NET) #if defined(CONFIG_CMD_NET)