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mmc: zynq: Sync with upstream DT binding

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Versal NET is not in production yet that's why no need to keep backward
compatible with previously used compatible string.

Link: https://lore.kernel.org/r/20230403102551.3763054-2-sai.krishna.potthuri@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0d355f4fbaf6a3521d41ee43f17dde2515ff7ab7.1684311766.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-05-17 10:22:48 +02:00
parent 3e95bf9b76
commit ed99a77b2a
1 changed files with 5 additions and 5 deletions
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10
drivers/mmc/zynq_sdhci.c
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@ -873,7 +873,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
if (ret) if (ret)
return ret; return ret;
} else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { device_is_compatible(dev, "xlnx,versal-net-emmc")) {
if (mmc->clock >= MIN_PHY_CLK_HZ) if (mmc->clock >= MIN_PHY_CLK_HZ)
if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL; iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
@ -948,7 +948,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
} }
if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { device_is_compatible(dev, "xlnx,versal-net-emmc")) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i]; clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
@ -1102,7 +1102,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
} }
} }
#endif #endif
if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) if (device_is_compatible(dev, "xlnx,versal-net-emmc"))
priv->internal_phy_reg = true; priv->internal_phy_reg = true;
ret = clk_get_by_index(dev, 0, &clk); ret = clk_get_by_index(dev, 0, &clk);
@ -1136,7 +1136,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks |= SDHCI_QUIRK_NO_1_8_V; host->quirks |= SDHCI_QUIRK_NO_1_8_V;
if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) && if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) device_is_compatible(dev, "xlnx,versal-net-emmc"))
host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400; host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
@ -1219,7 +1219,7 @@ static int arasan_sdhci_bind(struct udevice *dev)
static const struct udevice_id arasan_sdhci_ids[] = { static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" }, { .compatible = "arasan,sdhci-8.9a" },
{ .compatible = "xlnx,versal-net-5.1-emmc" }, { .compatible = "xlnx,versal-net-emmc" },
{ } { }
}; };