mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-13 20:36:02 +01:00
Merge tag 'u-boot-rockchip-20250220' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/24690 Please pull the fixes for rockchip platform: - Fix for rk3399 bob and kevin - Fix for sdram more than 4GB - Fix for dwc_eth on rk356x/rk3588 - Fix for sdmmc access on rk33080rock-s9
This commit is contained in:
Tom Rini
commit
ee69293e0d
@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \
|
||||
dtb-$(CONFIG_MACH_S700) += \
|
||||
s700-cubieboard7.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
|
||||
rk3036-sdk.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
|
||||
rk3128-evb.dtb
|
||||
|
||||
|
||||
@ -1,9 +1,5 @@
|
||||
#include "rk3036-u-boot.dtsi"
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&grf {
|
||||
bootph-all;
|
||||
};
|
||||
@ -11,3 +7,7 @@
|
||||
&pinctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
13
arch/arm/dts/rk3036-kylin-u-boot.dtsi
Normal file
13
arch/arm/dts/rk3036-kylin-u-boot.dtsi
Normal file
@ -0,0 +1,13 @@
|
||||
#include "rk3036-u-boot.dtsi"
|
||||
|
||||
&grf {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
@ -1,74 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3036.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SDK-RK3036";
|
||||
compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg-drv {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg";
|
||||
gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otg_vbus_drv>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-drv {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
vbus-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
vbus-supply = <&vcc5v0_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb_otg {
|
||||
otg_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,439 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/clock/rk3036-cru.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3036";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
i2c1 = &i2c1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
mmc0 = &emmc;
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "rockchip,rk3036-smp";
|
||||
|
||||
cpu0: cpu@f00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf00>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
816000 1000000
|
||||
>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
clock-latency = <40000>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
resets = <&cru SRST_CORE0>;
|
||||
};
|
||||
cpu1: cpu@f01 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf01>;
|
||||
resets = <&cru SRST_CORE1>;
|
||||
};
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@20078000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20078000 0x4000>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&cru ACLK_DMAC2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>;
|
||||
assigned-clock-rates = <594000000>;
|
||||
};
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
};
|
||||
|
||||
uart1: serial@20064000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x100>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
};
|
||||
|
||||
uart2: serial@20068000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20068000 0x100>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
pwm0: pwm@20050000 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050000 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_pin>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@20050010 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050010 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_pin>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@20050020 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050020 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_pin>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@20050030 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram: sram@10080000 {
|
||||
compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
|
||||
reg = <0x10080000 0x2000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10139000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x10139000 0x1000>,
|
||||
<0x1013a000 0x1000>,
|
||||
<0x1013c000 0x2000>,
|
||||
<0x1013e000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 0xf04>;
|
||||
};
|
||||
|
||||
grf: syscon@20008000 {
|
||||
compatible = "rockchip,rk3036-grf", "syscon";
|
||||
reg = <0x20008000 0x1000>;
|
||||
};
|
||||
|
||||
usb_otg: usb@10180000 {
|
||||
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
reg = <0x10180000 0x40000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG0>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "otg";
|
||||
g-np-tx-fifo-size = <16>;
|
||||
g-rx-fifo-size = <275>;
|
||||
g-tx-fifo-size = <256 128 128 64 64 32>;
|
||||
g-use-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host: usb@101c0000 {
|
||||
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
reg = <0x101c0000 0x40000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG1>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: dwmmc@1021c000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
clock-frequency = <37500000>;
|
||||
max-frequency = <37500000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
|
||||
dmas = <&pdma 12>;
|
||||
dma-names = "rx-tx";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x1021c000 0x4000>;
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
disable-wp;
|
||||
fifo-mode;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
default-sample-phase = <158>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
};
|
||||
|
||||
sdmmc: dwmmc@10214000 {
|
||||
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x10214000 0x4000>;
|
||||
clock-frequency = <37500000>;
|
||||
max-frequency = <37500000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3036-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@2007c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2007c000 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@20084000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20084000 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
emmc {
|
||||
/*
|
||||
* We run eMMC at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_none>;
|
||||
/*
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_up>;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart1 */
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <0 1 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <0 27 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@20056000 {
|
||||
compatible = "rockchip,rk3288-i2c";
|
||||
reg = <0x20056000 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -466,18 +466,18 @@ enum {
|
||||
/* GRF_GPIO4C_IOMUX */
|
||||
GRF_GPIO4C0_SEL_SHIFT = 0,
|
||||
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
|
||||
GRF_UART2DGBB_SIN = 2,
|
||||
GRF_UART2DBGB_SIN = 2,
|
||||
GRF_HDMII2C_SCL = 3,
|
||||
GRF_GPIO4C1_SEL_SHIFT = 2,
|
||||
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
|
||||
GRF_UART2DGBB_SOUT = 2,
|
||||
GRF_UART2DBGB_SOUT = 2,
|
||||
GRF_HDMII2C_SDA = 3,
|
||||
GRF_GPIO4C2_SEL_SHIFT = 4,
|
||||
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
|
||||
GRF_PWM_0 = 1,
|
||||
GRF_GPIO4C3_SEL_SHIFT = 6,
|
||||
GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
|
||||
GRF_UART2DGBC_SIN = 1,
|
||||
GRF_UART2DBGC_SIN = 1,
|
||||
GRF_GPIO4C4_SEL_SHIFT = 8,
|
||||
GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
|
||||
GRF_UART2DBGC_SOUT = 1,
|
||||
|
||||
@ -29,6 +29,7 @@ config ROCKCHIP_RK3036
|
||||
select CPU_V7A
|
||||
select SUPPORT_SPL
|
||||
select SPL
|
||||
imply OF_UPSTREAM
|
||||
imply USB_FUNCTION_ROCKUSB
|
||||
imply CMD_ROCKUSB
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <spl_gpio.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
@ -15,7 +16,6 @@
|
||||
#include <asm/arch-rockchip/gpio.h>
|
||||
#include <asm/arch-rockchip/grf_rk3399.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/printk.h>
|
||||
#include <power/regulator.h>
|
||||
@ -133,10 +133,31 @@ void board_debug_uart_init(void)
|
||||
GRF_GPIO3B7_SEL_MASK,
|
||||
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
|
||||
#else
|
||||
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
|
||||
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
|
||||
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD) &&
|
||||
(IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
|
||||
IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
|
||||
rk_setreg(&grf->io_vsel, 1 << 0);
|
||||
|
||||
/*
|
||||
* Let's enable these power rails here, we are already running
|
||||
* the SPI-Flash-based code.
|
||||
*/
|
||||
spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
|
||||
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
|
||||
GPIO_PULL_NORMAL);
|
||||
|
||||
spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
|
||||
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
|
||||
GPIO_PULL_NORMAL);
|
||||
}
|
||||
|
||||
/* Enable early UART2 channel C on the RK3399 */
|
||||
rk_clrsetreg(&grf->gpio4c_iomux,
|
||||
GRF_GPIO4C3_SEL_MASK,
|
||||
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
|
||||
GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT);
|
||||
rk_clrsetreg(&grf->gpio4c_iomux,
|
||||
GRF_GPIO4C4_SEL_MASK,
|
||||
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
|
||||
|
||||
@ -309,6 +309,8 @@ int dram_init_banksize(void)
|
||||
if (ram_top > SZ_4G && top < SZ_4G) {
|
||||
gd->bd->bi_dram[1].start = SZ_4G;
|
||||
gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
|
||||
} else if (ram_top > SZ_4G && top == SZ_4G) {
|
||||
gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
|
||||
}
|
||||
#else
|
||||
#ifdef CONFIG_SPL_OPTEE_IMAGE
|
||||
@ -476,6 +478,7 @@ int dram_init(void)
|
||||
debug("Cannot get DRAM size: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
gd->ram_base = ram.base;
|
||||
gd->ram_size = ram.size;
|
||||
debug("SDRAM base=%lx, size=%lx\n",
|
||||
(unsigned long)ram.base, (unsigned long)ram.size);
|
||||
@ -485,7 +488,8 @@ int dram_init(void)
|
||||
|
||||
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
|
||||
{
|
||||
unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
|
||||
/* Make sure U-Boot only uses the space below the 4G address boundary */
|
||||
u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G);
|
||||
|
||||
return (gd->ram_top > top) ? top : gd->ram_top;
|
||||
}
|
||||
|
||||
@ -35,6 +35,7 @@ CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_TPL_GPIO=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
|
||||
@ -36,6 +36,7 @@ CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_TPL_GPIO=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
|
||||
@ -11,7 +11,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-evb"
|
||||
CONFIG_ROCKCHIP_RK3036=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_SPL_STACK=0x10081fff
|
||||
@ -23,7 +23,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-evb.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
# CONFIG_SPL_FRAMEWORK is not set
|
||||
|
||||
@ -12,7 +12,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-kylin"
|
||||
CONFIG_ROCKCHIP_RK3036=y
|
||||
CONFIG_TARGET_KYLIN_RK3036=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-kylin.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
# CONFIG_SPL_FRAMEWORK is not set
|
||||
|
||||
@ -46,6 +46,10 @@ struct rockchip_platform_data {
|
||||
#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16))
|
||||
#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
|
||||
|
||||
#define DELAY_ENABLE(soc, tx, rx) \
|
||||
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
|
||||
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
|
||||
|
||||
#define RK3568_GRF_GMAC0_CON0 0x0380
|
||||
#define RK3568_GRF_GMAC0_CON1 0x0384
|
||||
#define RK3568_GRF_GMAC1_CON0 0x0388
|
||||
@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev,
|
||||
|
||||
regmap_write(data->grf, con1,
|
||||
RK3568_GMAC_PHY_INTF_SEL_RGMII |
|
||||
RK3568_GMAC_RXCLK_DLY_ENABLE |
|
||||
RK3568_GMAC_TXCLK_DLY_ENABLE);
|
||||
DELAY_ENABLE(RK3568, tx_delay, rx_delay));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -131,6 +134,10 @@ static int rk3568_set_gmac_speed(struct udevice *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RK3588_DELAY_ENABLE(id, tx, rx) \
|
||||
(((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \
|
||||
((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id)))
|
||||
|
||||
/* sys_grf */
|
||||
#define RK3588_GRF_GMAC_CON7 0x031c
|
||||
#define RK3588_GRF_GMAC_CON8 0x0320
|
||||
@ -189,8 +196,7 @@ static int rk3588_set_to_rgmii(struct udevice *dev,
|
||||
RK3588_GMAC_CLK_RGMII_MODE(id));
|
||||
|
||||
regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
|
||||
RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
|
||||
RK3588_GMAC_TXCLK_DLY_ENABLE(id));
|
||||
RK3588_DELAY_ENABLE(id, tx_delay, rx_delay));
|
||||
|
||||
regmap_write(data->grf, offset_con,
|
||||
RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
||||
|
||||
@ -14,23 +14,68 @@
|
||||
|
||||
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
|
||||
{
|
||||
.num = 2,
|
||||
.pin = 12,
|
||||
.reg = 0x24,
|
||||
.bit = 8,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio2_b7_sel */
|
||||
.num = 2,
|
||||
.pin = 15,
|
||||
.reg = 0x28,
|
||||
.bit = 0,
|
||||
.mask = 0x7
|
||||
}, {
|
||||
/* gpio2_c7_sel */
|
||||
.num = 2,
|
||||
.pin = 23,
|
||||
.reg = 0x30,
|
||||
.bit = 14,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b1_sel */
|
||||
.num = 3,
|
||||
.pin = 9,
|
||||
.reg = 0x44,
|
||||
.bit = 2,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b2_sel */
|
||||
.num = 3,
|
||||
.pin = 10,
|
||||
.reg = 0x44,
|
||||
.bit = 4,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b3_sel */
|
||||
.num = 3,
|
||||
.pin = 11,
|
||||
.reg = 0x44,
|
||||
.bit = 6,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b4_sel */
|
||||
.num = 3,
|
||||
.pin = 12,
|
||||
.reg = 0x44,
|
||||
.bit = 8,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b5_sel */
|
||||
.num = 3,
|
||||
.pin = 13,
|
||||
.reg = 0x44,
|
||||
.bit = 10,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b6_sel */
|
||||
.num = 3,
|
||||
.pin = 14,
|
||||
.reg = 0x44,
|
||||
.bit = 12,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
/* gpio3_b7_sel */
|
||||
.num = 3,
|
||||
.pin = 15,
|
||||
.reg = 0x44,
|
||||
.bit = 14,
|
||||
.mask = 0x3
|
||||
},
|
||||
};
|
||||
|
||||
@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
|
||||
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
|
||||
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
|
||||
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
|
||||
IOMUX_WIDTH_3BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_WIDTH_3BIT,
|
||||
0),
|
||||
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
|
||||
|
||||
@ -74,6 +74,23 @@
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
/*
|
||||
* HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc.
|
||||
* This is modeled as an always-on active low fixed regulator.
|
||||
*/
|
||||
vcc_sd: regulator-3v3-vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_2030>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: regulator-5v0-vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
@ -181,6 +198,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_2030: sdmmc-2030 {
|
||||
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi {
|
||||
wifi_reg_on: wifi-reg-on {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
@ -233,7 +256,7 @@
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -1,185 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_GPLL 3
|
||||
#define ARMCLK 4
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_GPU 64
|
||||
#define SCLK_SPI 65
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_NANDC 76
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_OTGPHY0 93
|
||||
#define SCLK_LCDC 100
|
||||
#define SCLK_HDMI 109
|
||||
#define SCLK_HEVC 111
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_PVTM_VIDEO 125
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF 152
|
||||
#define SCLK_SFC 160
|
||||
|
||||
#define DCLK_LCDC 190
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC2 194
|
||||
#define ACLK_LCDC 197
|
||||
#define ACLK_VIO 203
|
||||
#define ACLK_VCODEC 208
|
||||
#define ACLK_CPU 209
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_SPI 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_HDMI 360
|
||||
#define PCLK_CPU 362
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_DDRUPCTL 364
|
||||
#define PCLK_WDT 368
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_OTG0 449
|
||||
#define HCLK_OTG1 450
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_I2S 462
|
||||
#define HCLK_LCDC 465
|
||||
#define HCLK_ROM 467
|
||||
#define HCLK_VIO_BUS 472
|
||||
#define HCLK_VCODEC 476
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
#define SRST_CORE0_DBG 4
|
||||
#define SRST_CORE1_DBG 5
|
||||
#define SRST_CORE0_POR 8
|
||||
#define SRST_CORE1_POR 9
|
||||
#define SRST_L2C 12
|
||||
#define SRST_TOPDBG 13
|
||||
#define SRST_STRC_SYS_A 14
|
||||
#define SRST_PD_CORE_NIU 15
|
||||
|
||||
#define SRST_TIMER2 16
|
||||
#define SRST_CPUSYS_H 17
|
||||
#define SRST_AHB2APB_H 19
|
||||
#define SRST_TIMER3 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_PERI_NIU 23
|
||||
#define SRST_I2S 24
|
||||
#define SRST_DDR_PLL 25
|
||||
#define SRST_GPU_DLL 26
|
||||
#define SRST_TIMER0 27
|
||||
#define SRST_TIMER1 28
|
||||
#define SRST_CORE_DLL 29
|
||||
#define SRST_EFUSE_P 30
|
||||
#define SRST_ACODEC_P 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_SFC 47
|
||||
|
||||
#define SRST_PWM0 48
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PERIPHSYS_A 57
|
||||
#define SRST_PERIPHSYS_H 58
|
||||
#define SRST_PERIPHSYS_P 59
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA2 64
|
||||
#define SRST_MAC 66
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_MMC0 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI0 84
|
||||
#define SRST_WDT 86
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_BUS_H 99
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_USBPOR 105
|
||||
|
||||
#define SRST_VCODEC_A 112
|
||||
#define SRST_VCODEC_H 113
|
||||
#define SRST_VIO1_A 114
|
||||
#define SRST_HEVC 115
|
||||
#define SRST_VCODEC_NIU_A 116
|
||||
#define SRST_LCDC1_A 117
|
||||
#define SRST_LCDC1_H 118
|
||||
#define SRST_LCDC1_D 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU_A 122
|
||||
|
||||
#define SRST_DBG_P 131
|
||||
|
||||
#endif
|
||||
@ -1,381 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_NPLL 5
|
||||
#define ARMCLK 6
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_GPU 64
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_SPI1 66
|
||||
#define SCLK_SPI2 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO0 69
|
||||
#define SCLK_SDIO1 70
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_TSADC 72
|
||||
#define SCLK_SARADC 73
|
||||
#define SCLK_PS2C 74
|
||||
#define SCLK_NANDC0 75
|
||||
#define SCLK_NANDC1 76
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_UART3 80
|
||||
#define SCLK_UART4 81
|
||||
#define SCLK_I2S0 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_SPDIF8CH 84
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_TIMER4 89
|
||||
#define SCLK_TIMER5 90
|
||||
#define SCLK_TIMER6 91
|
||||
#define SCLK_HSADC 92
|
||||
#define SCLK_OTGPHY0 93
|
||||
#define SCLK_OTGPHY1 94
|
||||
#define SCLK_OTGPHY2 95
|
||||
#define SCLK_OTG_ADP 96
|
||||
#define SCLK_HSICPHY480M 97
|
||||
#define SCLK_HSICPHY12M 98
|
||||
#define SCLK_MACREF 99
|
||||
#define SCLK_LCDC_PWM0 100
|
||||
#define SCLK_LCDC_PWM1 101
|
||||
#define SCLK_MAC_RX 102
|
||||
#define SCLK_MAC_TX 103
|
||||
#define SCLK_EDP_24M 104
|
||||
#define SCLK_EDP 105
|
||||
#define SCLK_RGA 106
|
||||
#define SCLK_ISP 107
|
||||
#define SCLK_ISP_JPE 108
|
||||
#define SCLK_HDMI_HDCP 109
|
||||
#define SCLK_HDMI_CEC 110
|
||||
#define SCLK_HEVC_CABAC 111
|
||||
#define SCLK_HEVC_CORE 112
|
||||
#define SCLK_I2S0_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO0_DRV 115
|
||||
#define SCLK_SDIO1_DRV 116
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO0_SAMPLE 119
|
||||
#define SCLK_SDIO1_SAMPLE 120
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_USBPHY480M_SRC 122
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_CRYPTO 125
|
||||
#define SCLK_MIPIDSI_24M 126
|
||||
#define SCLK_VIP_OUT 127
|
||||
|
||||
#define SCLK_MAC_PLL 150
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF_OUT 152
|
||||
|
||||
#define DCLK_VOP0 190
|
||||
#define DCLK_VOP1 191
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_GPU 192
|
||||
#define ACLK_DMAC1 193
|
||||
#define ACLK_DMAC2 194
|
||||
#define ACLK_MMU 195
|
||||
#define ACLK_GMAC 196
|
||||
#define ACLK_VOP0 197
|
||||
#define ACLK_VOP1 198
|
||||
#define ACLK_CRYPTO 199
|
||||
#define ACLK_RGA 200
|
||||
#define ACLK_RGA_NIU 201
|
||||
#define ACLK_IEP 202
|
||||
#define ACLK_VIO0_NIU 203
|
||||
#define ACLK_VIP 204
|
||||
#define ACLK_ISP 205
|
||||
#define ACLK_VIO1_NIU 206
|
||||
#define ACLK_HEVC 207
|
||||
#define ACLK_VCODEC 208
|
||||
#define ACLK_CPU 209
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_GPIO4 324
|
||||
#define PCLK_GPIO5 325
|
||||
#define PCLK_GPIO6 326
|
||||
#define PCLK_GPIO7 327
|
||||
#define PCLK_GPIO8 328
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_SGRF 330
|
||||
#define PCLK_PMU 331
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_I2C3 335
|
||||
#define PCLK_I2C4 336
|
||||
#define PCLK_I2C5 337
|
||||
#define PCLK_SPI0 338
|
||||
#define PCLK_SPI1 339
|
||||
#define PCLK_SPI2 340
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_UART3 344
|
||||
#define PCLK_UART4 345
|
||||
#define PCLK_TSADC 346
|
||||
#define PCLK_SARADC 347
|
||||
#define PCLK_SIM 348
|
||||
#define PCLK_GMAC 349
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_RKPWM 351
|
||||
#define PCLK_PS2C 352
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_TZPC 354
|
||||
#define PCLK_EDP_CTRL 355
|
||||
#define PCLK_MIPI_DSI0 356
|
||||
#define PCLK_MIPI_DSI1 357
|
||||
#define PCLK_MIPI_CSI 358
|
||||
#define PCLK_LVDS_PHY 359
|
||||
#define PCLK_HDMI_CTRL 360
|
||||
#define PCLK_VIO2_H2P 361
|
||||
#define PCLK_CPU 362
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_DDRUPCTL0 364
|
||||
#define PCLK_PUBL0 365
|
||||
#define PCLK_DDRUPCTL1 366
|
||||
#define PCLK_PUBL1 367
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_EFUSE256 369
|
||||
#define PCLK_EFUSE1024 370
|
||||
#define PCLK_ISP_IN 371
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_GPS 448
|
||||
#define HCLK_OTG0 449
|
||||
#define HCLK_USBHOST0 450
|
||||
#define HCLK_USBHOST1 451
|
||||
#define HCLK_HSIC 452
|
||||
#define HCLK_NANDC0 453
|
||||
#define HCLK_NANDC1 454
|
||||
#define HCLK_TSP 455
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO0 457
|
||||
#define HCLK_SDIO1 458
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_HSADC 460
|
||||
#define HCLK_CRYPTO 461
|
||||
#define HCLK_I2S0 462
|
||||
#define HCLK_SPDIF 463
|
||||
#define HCLK_SPDIF8CH 464
|
||||
#define HCLK_VOP0 465
|
||||
#define HCLK_VOP1 466
|
||||
#define HCLK_ROM 467
|
||||
#define HCLK_IEP 468
|
||||
#define HCLK_ISP 469
|
||||
#define HCLK_RGA 470
|
||||
#define HCLK_VIO_AHB_ARBI 471
|
||||
#define HCLK_VIO_NIU 472
|
||||
#define HCLK_VIP 473
|
||||
#define HCLK_VIO2_H2P 474
|
||||
#define HCLK_HEVC 475
|
||||
#define HCLK_VCODEC 476
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
#define SRST_CORE2 2
|
||||
#define SRST_CORE3 3
|
||||
#define SRST_CORE0_PO 4
|
||||
#define SRST_CORE1_PO 5
|
||||
#define SRST_CORE2_PO 6
|
||||
#define SRST_CORE3_PO 7
|
||||
#define SRST_PDCORE_STRSYS 8
|
||||
#define SRST_PDBUS_STRSYS 9
|
||||
#define SRST_L2C 10
|
||||
#define SRST_TOPDBG 11
|
||||
#define SRST_CORE0_DBG 12
|
||||
#define SRST_CORE1_DBG 13
|
||||
#define SRST_CORE2_DBG 14
|
||||
#define SRST_CORE3_DBG 15
|
||||
|
||||
#define SRST_PDBUG_AHB_ARBITOR 16
|
||||
#define SRST_EFUSE256 17
|
||||
#define SRST_DMAC1 18
|
||||
#define SRST_INTMEM 19
|
||||
#define SRST_ROM 20
|
||||
#define SRST_SPDIF8CH 21
|
||||
#define SRST_TIMER 22
|
||||
#define SRST_I2S0 23
|
||||
#define SRST_SPDIF 24
|
||||
#define SRST_TIMER0 25
|
||||
#define SRST_TIMER1 26
|
||||
#define SRST_TIMER2 27
|
||||
#define SRST_TIMER3 28
|
||||
#define SRST_TIMER4 29
|
||||
#define SRST_TIMER5 30
|
||||
#define SRST_EFUSE 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_GPIO4 36
|
||||
#define SRST_GPIO5 37
|
||||
#define SRST_GPIO6 38
|
||||
#define SRST_GPIO7 39
|
||||
#define SRST_GPIO8 40
|
||||
#define SRST_I2C0 42
|
||||
#define SRST_I2C1 43
|
||||
#define SRST_I2C2 44
|
||||
#define SRST_I2C3 45
|
||||
#define SRST_I2C4 46
|
||||
#define SRST_I2C5 47
|
||||
|
||||
#define SRST_DWPWM 48
|
||||
#define SRST_MMC_PERI 49
|
||||
#define SRST_PERIPH_MMU 50
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_TPIU 53
|
||||
#define SRST_PMU_APB 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PMU 56
|
||||
#define SRST_PERIPH_AXI 57
|
||||
#define SRST_PERIPH_AHB 58
|
||||
#define SRST_PERIPH_APB 59
|
||||
#define SRST_PERIPH_NIU 60
|
||||
#define SRST_PDPERI_AHB_ARBI 61
|
||||
#define SRST_EMEM 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMAC2 64
|
||||
#define SRST_MAC 66
|
||||
#define SRST_GPS 67
|
||||
#define SRST_RKPWM 69
|
||||
#define SRST_CCP 71
|
||||
#define SRST_USBHOST0 72
|
||||
#define SRST_HSIC 73
|
||||
#define SRST_HSIC_AUX 74
|
||||
#define SRST_HSIC_PHY 75
|
||||
#define SRST_HSADC 76
|
||||
#define SRST_NANDC0 77
|
||||
#define SRST_NANDC1 78
|
||||
|
||||
#define SRST_TZPC 80
|
||||
#define SRST_SPI0 83
|
||||
#define SRST_SPI1 84
|
||||
#define SRST_SPI2 85
|
||||
#define SRST_SARADC 87
|
||||
#define SRST_PDALIVE_NIU 88
|
||||
#define SRST_PDPMU_INTMEM 89
|
||||
#define SRST_PDPMU_NIU 90
|
||||
#define SRST_SGRF 91
|
||||
|
||||
#define SRST_VIO_ARBI 96
|
||||
#define SRST_RGA_NIU 97
|
||||
#define SRST_VIO0_NIU_AXI 98
|
||||
#define SRST_VIO_NIU_AHB 99
|
||||
#define SRST_LCDC0_AXI 100
|
||||
#define SRST_LCDC0_AHB 101
|
||||
#define SRST_LCDC0_DCLK 102
|
||||
#define SRST_VIO1_NIU_AXI 103
|
||||
#define SRST_VIP 104
|
||||
#define SRST_RGA_CORE 105
|
||||
#define SRST_IEP_AXI 106
|
||||
#define SRST_IEP_AHB 107
|
||||
#define SRST_RGA_AXI 108
|
||||
#define SRST_RGA_AHB 109
|
||||
#define SRST_ISP 110
|
||||
#define SRST_EDP 111
|
||||
|
||||
#define SRST_VCODEC_AXI 112
|
||||
#define SRST_VCODEC_AHB 113
|
||||
#define SRST_VIO_H2P 114
|
||||
#define SRST_MIPIDSI0 115
|
||||
#define SRST_MIPIDSI1 116
|
||||
#define SRST_MIPICSI 117
|
||||
#define SRST_LVDS_PHY 118
|
||||
#define SRST_LVDS_CON 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_HDMI 121
|
||||
#define SRST_CORE_PVTM 124
|
||||
#define SRST_GPU_PVTM 125
|
||||
|
||||
#define SRST_MMC0 128
|
||||
#define SRST_SDIO0 129
|
||||
#define SRST_SDIO1 130
|
||||
#define SRST_EMMC 131
|
||||
#define SRST_USBOTG_AHB 132
|
||||
#define SRST_USBOTG_PHY 133
|
||||
#define SRST_USBOTG_CON 134
|
||||
#define SRST_USBHOST0_AHB 135
|
||||
#define SRST_USBHOST0_PHY 136
|
||||
#define SRST_USBHOST0_CON 137
|
||||
#define SRST_USBHOST1_AHB 138
|
||||
#define SRST_USBHOST1_PHY 139
|
||||
#define SRST_USBHOST1_CON 140
|
||||
#define SRST_USB_ADP 141
|
||||
#define SRST_ACC_EFUSE 142
|
||||
|
||||
#define SRST_CORESIGHT 144
|
||||
#define SRST_PD_CORE_AHB_NOC 145
|
||||
#define SRST_PD_CORE_APB_NOC 146
|
||||
#define SRST_PD_CORE_MP_AXI 147
|
||||
#define SRST_GIC 148
|
||||
#define SRST_LCDC_PWM0 149
|
||||
#define SRST_LCDC_PWM1 150
|
||||
#define SRST_VIO0_H2P_BRG 151
|
||||
#define SRST_VIO1_H2P_BRG 152
|
||||
#define SRST_RGA_H2P_BRG 153
|
||||
#define SRST_HEVC 154
|
||||
#define SRST_TSADC 159
|
||||
|
||||
#define SRST_DDRPHY0 160
|
||||
#define SRST_DDRPHY0_APB 161
|
||||
#define SRST_DDRCTRL0 162
|
||||
#define SRST_DDRCTRL0_APB 163
|
||||
#define SRST_DDRPHY0_CTRL 164
|
||||
#define SRST_DDRPHY1 165
|
||||
#define SRST_DDRPHY1_APB 166
|
||||
#define SRST_DDRCTRL1 167
|
||||
#define SRST_DDRCTRL1_APB 168
|
||||
#define SRST_DDRPHY1_CTRL 169
|
||||
#define SRST_DDRMSCH0 170
|
||||
#define SRST_DDRMSCH1 171
|
||||
#define SRST_CRYPTO 174
|
||||
#define SRST_C2C_HOST 175
|
||||
|
||||
#define SRST_LCDC1_AXI 176
|
||||
#define SRST_LCDC1_AHB 177
|
||||
#define SRST_LCDC1_DCLK 178
|
||||
#define SRST_UART0 179
|
||||
#define SRST_UART1 180
|
||||
#define SRST_UART2 181
|
||||
#define SRST_UART3 182
|
||||
#define SRST_UART4 183
|
||||
#define SRST_SIMC 186
|
||||
#define SRST_PS2C 187
|
||||
#define SRST_TSP 188
|
||||
#define SRST_TSP_CLKIN0 189
|
||||
#define SRST_TSP_CLKIN1 190
|
||||
#define SRST_TSP_27M 191
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user