Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline

arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi

@@ -2,7 +2,7 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_agilex-u-boot.dtsi"
@@ -11,6 +11,15 @@
 	aliases {
 		spi0 = &qspi;
 		i2c0 = &i2c1;
+		freeze_br0 = &freeze_controller;
+	};
+
+	soc {
+		freeze_controller: freeze_controller@f9000450 {
+			compatible = "altr,freeze-bridge-controller";
+			reg = <0xf9000450 0x00000010>;
+			status = "disabled";
+		};
 	};
 
 	memory {

arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi

@@ -2,7 +2,7 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_stratix10-u-boot.dtsi"
@@ -10,6 +10,15 @@
 /{
 	aliases {
 		spi0 = &qspi;
+		freeze_br0 = &freeze_controller;
+	};
+
+	soc {
+		freeze_controller: freeze_controller@f9000450 {
+			compatible = "altr,freeze-bridge-controller";
+			reg = <0xf9000450 0x00000010>;
+			status = "disabled";
+		};
 	};
 };
 

arch/arm/dts/socfpga_stratix10_socdk.dts

@@ -92,7 +92,7 @@
 	broken-cd;
 	bus-width = <4>;
 	drvsel = <3>;
-	smplsel = <0>;
+	smplsel = <2>;
 };
 
 &qspi {

arch/arm/mach-socfpga/timer_s10.c

@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2022 Intel Corporation <www.intel.com>
  *
  */
 
 #include <common.h>
 #include <init.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
@@ -26,3 +27,34 @@ int timer_init(void)
 #endif
 	return 0;
 }
+
+__always_inline u64 __get_time_stamp(void)
+{
+	u64 cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+	return cntpct;
+}
+
+__always_inline uint64_t __usec_to_tick(unsigned long usec)
+{
+	u64 tick = usec;
+	u64 cntfrq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+	tick *= cntfrq;
+	do_div(tick, 1000000);
+
+	return tick;
+}
+
+__always_inline void __udelay(unsigned long usec)
+{
+	/* get current timestamp */
+	u64 tmp = __get_time_stamp() + __usec_to_tick(usec);
+
+	while (__get_time_stamp() < tmp + 1)	/* loop till event */
+		;
+}

drivers/cache/cache-ncore.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  *
  */
 #include <dm.h>
@@ -81,8 +81,8 @@ static void ncore_ccu_init_dirs(void __iomem *base)
 				hang();
 			}
 
-			/* Enable snoop filter, a bit per snoop filter */
+			/* Disable snoop filter, a bit per snoop filter */
-			setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+			clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
 				     BIT(f));
 		}
 	}

drivers/ddr/altera/sdram_n5x.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
  *
  */
 

drivers/ddr/altera/sdram_s10.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
  *
  */
 
@@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev)
 			DDR_SCH_DEVTODEV);
 
 	/* assigning the SDRAM size */
-	unsigned long long size = sdram_calculate_size(plat);
+	phys_size_t size = sdram_calculate_size(plat);
 	/* If the size is invalid, use default Config size */
 	if (size <= 0)
 		hw_size = PHYS_SDRAM_1_SIZE;

drivers/ddr/altera/sdram_soc64.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
  *
  */
 
@@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
 {
 	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 
-	phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+	phys_size_t size = (phys_size_t)1 <<
+			(DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +

drivers/ddr/altera/sdram_soc64.h

@@ -53,7 +53,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
+#define DDR_HMC_RSTHANDSHAKE_MASK		0x0000000f
 #define DDR_HMC_CORE2SEQ_INT_REQ		0xF
 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f

include/configs/socfpga_vining_fpga.h

@@ -116,7 +116,8 @@
 	"addargs=run addcons addmtd addmisc\0"				\
 	"ubiload="							\
 		"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; "		\
-		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
+		"ubifsload ${kernel_addr_r} /boot/${bootfile} ; "	\
+		"ubifsumount ; ubi detach\0"				\
 	"netload="							\
 		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
 	"miscargs=nohlt panic=1\0"					\