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mips: octeon: Add cvmx-agl.c
Import cvmx-agl.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Stefan Roese
parent
6fd320cd5c
commit
f1ee39438d
216
arch/mips/mach-octeon/cvmx-agl.c
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216
arch/mips/mach-octeon/cvmx-agl.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Functions for RGMII (MGMT) initialization, configuration,
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* and monitoring.
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*/
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#include <log.h>
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#include <time.h>
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#include <linux/delay.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-csr.h>
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#include <mach/cvmx-bootmem.h>
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#include <mach/octeon-model.h>
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#include <mach/cvmx-fuse.h>
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#include <mach/octeon-feature.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/cvmx-pcie.h>
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#include <mach/cvmx-coremask.h>
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#include <mach/cvmx-pki.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-board.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-agl.h>
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#include <mach/cvmx-agl-defs.h>
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/*
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* @param port to enable
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_agl_enable(int port)
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{
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cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl;
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rxx_frm_ctl.u64 = 0;
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rxx_frm_ctl.s.pre_align = 1;
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/* When set, disables the length check for non-min sized pkts with
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* padding in the client data
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*/
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rxx_frm_ctl.s.pad_len = 1;
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/* When set, disables the length check for VLAN pkts */
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rxx_frm_ctl.s.vlan_len = 1;
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/* When set, PREAMBLE checking is less strict */
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rxx_frm_ctl.s.pre_free = 1;
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/* Control Pause Frames can match station SMAC */
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rxx_frm_ctl.s.ctl_smac = 0;
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/* Control Pause Frames can match globally assign Multicast address */
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rxx_frm_ctl.s.ctl_mcst = 1;
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rxx_frm_ctl.s.ctl_bck = 1; /* Forward pause information to TX block */
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rxx_frm_ctl.s.ctl_drp = 1; /* Drop Control Pause Frames */
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rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */
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/* This port is configured to send PREAMBLE+SFD to begin every frame.
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* GMX checks that the PREAMBLE is sent correctly
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*/
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rxx_frm_ctl.s.pre_chk = 1;
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csr_wr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
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return 0;
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}
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cvmx_helper_link_info_t cvmx_agl_link_get(int port)
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{
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cvmx_helper_link_info_t result;
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int interface, port_index;
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/* Fake IPD port is used on some older models. */
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if (port < 0)
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return __cvmx_helper_board_link_get(port);
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/* Simulator does not have PHY, use some defaults. */
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interface = cvmx_helper_get_interface_num(port);
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port_index = cvmx_helper_get_interface_index_num(port);
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if (cvmx_helper_get_port_force_link_up(interface, port_index)) {
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result.u64 = 0;
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result.s.full_duplex = 1;
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result.s.link_up = 1;
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result.s.speed = 1000;
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return result;
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}
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return __cvmx_helper_board_link_get(port);
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}
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/*
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* Set MII/RGMII link based on mode.
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*
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* @param port interface port to set the link.
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* @param link_info Link status
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*
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* @return 0 on success and 1 on failure
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*/
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int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info)
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{
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cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
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/* Disable GMX before we make any changes. */
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agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
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agl_gmx_prtx.s.en = 0;
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agl_gmx_prtx.s.tx_en = 0;
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agl_gmx_prtx.s.rx_en = 0;
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csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
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u64 one_second = 0x1000000; /* todo: this needs checking */
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/* Wait for GMX to be idle */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port),
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cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==,
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1, one_second) ||
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CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port),
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cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==,
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1, one_second)) {
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debug("AGL%d: Timeout waiting for GMX to be idle\n",
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port);
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return -1;
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}
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}
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agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
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/* Set duplex mode */
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if (!link_info.s.link_up)
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agl_gmx_prtx.s.duplex = 1; /* Force full duplex on down links */
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else
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agl_gmx_prtx.s.duplex = link_info.s.full_duplex;
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switch (link_info.s.speed) {
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case 10:
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agl_gmx_prtx.s.speed = 0;
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agl_gmx_prtx.s.slottime = 0;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
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agl_gmx_prtx.s.speed_msb = 1;
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agl_gmx_prtx.s.burst = 1;
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}
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break;
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case 100:
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agl_gmx_prtx.s.speed = 0;
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agl_gmx_prtx.s.slottime = 0;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
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agl_gmx_prtx.s.speed_msb = 0;
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agl_gmx_prtx.s.burst = 1;
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}
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break;
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case 1000:
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/* 1000 MBits is only supported on 6XXX chips */
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
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agl_gmx_prtx.s.speed_msb = 0;
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agl_gmx_prtx.s.speed = 1;
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agl_gmx_prtx.s.slottime =
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1; /* Only matters for half-duplex */
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agl_gmx_prtx.s.burst = agl_gmx_prtx.s.duplex;
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}
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break;
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/* No link */
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case 0:
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default:
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break;
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}
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/* Write the new GMX setting with the port still disabled. */
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csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
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/* Read GMX CFG again to make sure the config is completed. */
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agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
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cvmx_agl_gmx_txx_clk_t agl_clk;
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cvmx_agl_prtx_ctl_t prt_ctl;
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prt_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
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agl_clk.u64 = csr_rd(CVMX_AGL_GMX_TXX_CLK(port));
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/* MII (both speeds) and RGMII 1000 setting */
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agl_clk.s.clk_cnt = 1;
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/* Check other speeds for RGMII mode */
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if (prt_ctl.s.mode == 0 || OCTEON_IS_OCTEON3()) {
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if (link_info.s.speed == 10)
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agl_clk.s.clk_cnt = 50;
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else if (link_info.s.speed == 100)
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agl_clk.s.clk_cnt = 5;
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}
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csr_wr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64);
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}
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/* Enable transmit and receive ports */
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agl_gmx_prtx.s.tx_en = 1;
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agl_gmx_prtx.s.rx_en = 1;
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csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
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/* Enable the link. */
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agl_gmx_prtx.s.en = 1;
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csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
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if (OCTEON_IS_OCTEON3()) {
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union cvmx_agl_prtx_ctl agl_prtx_ctl;
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/* Enable the interface, set clkrst */
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agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
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agl_prtx_ctl.s.clkrst = 1;
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csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
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csr_rd(CVMX_AGL_PRTX_CTL(port));
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agl_prtx_ctl.s.enable = 1;
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csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
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/* Read the value back to force the previous write */
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csr_rd(CVMX_AGL_PRTX_CTL(port));
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}
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return 0;
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}
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