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omap3:clock: configure GFX clock to 200MHz for AM/DM37x

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AM/DM37x is another OMAP3 variant, where the GFX clock has been
boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change.

HW Errata: Due to dependency of TV out clock of 54MHz, it is not
possible to configure GFX to 192MHz. So as per HW errats, the
recommended GFX clock is 200MHz (=CORE_CLK/2).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Vaibhav Hiremath 2011-09-03 21:29:59 -04:00 committed by Albert ARIBAUD
parent f62b1257f2
commit f4dac3e16c
2 changed files with 2 additions and 1 deletions
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2
arch/arm/cpu/armv7/omap3/clock.c
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@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
/* L3 */ /* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
/* GFX */ /* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
/* RESET MGR */ /* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */

1
arch/arm/include/asm/arch-omap3/clocks_omap3.h
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@ -39,6 +39,7 @@
#define CORE_L4_DIV 2 /* 83MHz : L4 */ #define CORE_L4_DIV 2 /* 83MHz : L4 */
#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
/* PER DPLL */ /* PER DPLL */