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mips: octeon: mrvl, octeon-nic23.dts: Add ethernet DT support
Add the Octeon ethernet (BGX) and SFP DT nodes to the NIC23 dts file to enable ethernet support on this board. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
03b5f836b6
commit
f858bcccf4
@ -118,11 +118,208 @@
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&i2c0 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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sfp0eeprom: eeprom@50 {
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compatible = "atmel,24c01";
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reg = <0x50>;
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};
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sfp0alerts: eeprom@51 {
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compatible = "atmel,24c01";
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reg = <0x51>;
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};
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};
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&i2c1 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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vitesse@10 {
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compatible = "vitesse,vsc7224";
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reg = <0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Note that reset is active high with this device */
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reset = <&gpio 7 0>;
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/* LoS pin can be pulled low when there is a loss of signal */
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los = <&gpio 6 0>;
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vitesse,reg-init =
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/* Clear all masks */
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/* Page select FSYNC0 (0x30) */
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<0x7f 0x0030>,
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/* Set FSYNC0 for 10.3125Gbps */
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<0x80 0x2841>, /* See Table 3. */
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<0x81 0x0008>,
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<0x82 0xc000>,
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<0x83 0x0010>,
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<0x84 0x1d00>,
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/* All channels Rx settings set equally */
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<0x7f 0x0050>,
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/* Shrink EQ_BUFF */
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<0x82 0x0014>,
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/* Set EQVGA_ADAP = 1 (enable EQVGA circuitry),
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* USE_UNIT_GAIN = 1 (EQVGA is in unity gain),
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* USE_LPF = 0 (VGA adapt not using LPF),
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* USE_EQVGA = 1
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<0x89 0x7f13>,
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/* Select min DFE Delay (DFE_DELAY) */
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<0x90 0x5785>,
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/* Set DFE 1-3 limit (DXMAX) = 32dec,
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* AP Max limit = 127 decimal
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*/
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<0x92 0x207f>,
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/* Set AP Min limit = 32 decimal */
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<0x93 0x2000>,
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/* Set DFE Averaging to the slowest (DFE_AVG) */
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<0x94 0x0031>,
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/* Set Inductor Bypass OD_IND_BYP = 0 & fastest Rise/Fall */
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<0x9c 0x0000>,
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/* Setting DFE Boost = none. Must set for
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* rev C (if DFE in adapt mode)
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*/
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<0xaa 0x0888>,
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/* Setting EQ Min = 8 & Max limit = 72 dec.
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* Must set for rev C, otherwise EQ is 0
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* (if EQ is in adaptive mode)
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*/
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<0xa8 0x2408>,
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/* Setting EQVGA = 96, when in EQVGA manual mode */
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<0xa9 0x0060>,
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/* Setting SW_BFOCM, bits 15:14 to 01 */
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<0x87 0x4021>,
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/* Turn off adaptive input equalization
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* and VGA adaptive algorithm control.
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*/
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<0x89 0x7313>,
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/* Turn on adaptive input equalization
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* and VGA adaptive algorithm control.
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*/
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<0x89 0x7f13>;
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vitesse-channel@0 {
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compatible = "vitesse,vsc7224-channel";
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reg = <0>;
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direction-tx;
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sfp-mac = <ð0>;
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/* TAP settings. The format of this is as
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* follows:
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* - cable length in meters, 0 = active or
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* optical module
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* - maintap value
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* - pretap value
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* - posttap value
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*
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* For the cable length, the value will apply
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* for that cable length and greater until the
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* next largest cable length specified. These
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* values must be ordered first by channel mask
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* then by cable length. These are typically
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* set for the transmit channels, not the
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* receive channels.
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*/
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taps = <0 0x0013 0x000f 0x0000>,
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<1 0x001f 0x000f 0x0004>,
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<3 0x0014 0x000b 0x0004>,
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<5 0x0014 0x0009 0x0006>,
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<7 0x0014 0x000f 0x0000>,
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<10 0x0012 0x000b 0x0013>;
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};
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vitesse-channel@1 {
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compatible = "vitesse,vsc7224-channel";
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reg = <1>;
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/* Ignore mod_abs and module */
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direction-rx;
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sfp-mac = <ð0>;
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/* Disable pre-tap */
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pretap-disable;
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/* Disable post-tap */
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posttap-disable;
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/* Taps has the following fields:
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* - cable length (ignored for rx)
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* - main tap value
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* - pre tap value
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* - post tap value
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*
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* NOTE: if taps are disabled then they
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* are not programmed.
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*/
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taps = <0 0x0a 0x0b 0x10>;
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};
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vitesse-channel@2 {
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compatible = "vitesse,vsc7224-channel";
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reg = <2>;
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direction-tx;
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sfp-mac = <ð1>;
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/* TAP settings. The format of this is as
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* follows:
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* - cable length in meters, 0 = active or
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* optical module
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* - maintap value
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* - pretap value
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* - posttap value
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*
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* For the cable length, the value will apply
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* for that cable length and greater until the
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* next largest cable length specified. These
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* values must be ordered first by channel mask
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* then by cable length. These are typically
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* set for the transmit channels, not the
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* receive channels.
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*/
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taps = <0 0x0013 0x000f 0x0000>,
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<1 0x001f 0x000f 0x0004>,
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<3 0x0014 0x000b 0x0004>,
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<5 0x0014 0x0009 0x0006>,
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<7 0x0014 0x000f 0x0000>,
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<10 0x0012 0x000b 0x0013>;
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};
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vitesse-channel@3 {
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compatible = "vitesse,vsc7224-channel";
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reg = <3>;
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/* Ignore mod_abs and module */
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direction-rx;
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sfp-mac = <ð1>;
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/* Disable pre-tap */
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pretap-disable;
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/* Disable post-tap */
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posttap-disable;
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/* Taps has the following fields:
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* - cable length (ignored for rx)
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* - main tap value
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* - pre tap value
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* - post tap value
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*
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* NOTE: if taps are disabled then they
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* are not programmed.
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*/
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taps = <0 0x0a 0x0b 0x10>;
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};
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};
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sfp1eeprom: eeprom@50 {
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compatible = "atmel,24c01";
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reg = <0x50>;
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};
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sfp1alerts: eeprom@51 {
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compatible = "atmel,24c01";
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reg = <0x51>;
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};
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};
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&mmc {
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@ -151,6 +348,26 @@
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compatible = "marvell,pci-bootcmd";
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status = "okay";
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};
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sfp0: sfp-slot@0 {
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compatible = "ethernet,sfp-slot";
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tx_disable = <&gpio 16 0>;
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mod_abs = <&gpio 17 0>;
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tx_error = <&gpio 19 0>;
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rx_los = <&gpio 18 0>;
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eeprom = <&sfp0eeprom>;
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diag = <&sfp0alerts>;
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};
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sfp1: sfp-slot@1 {
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compatible = "ethernet,sfp-slot";
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tx_disable = <&gpio 21 0>;
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mod_abs = <&gpio 22 0>;
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tx_error = <&gpio 24 0>;
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rx_los = <&gpio 23 0>;
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eeprom = <&sfp1eeprom>;
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diag = <&sfp1alerts>;
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};
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};
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&spi {
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@ -160,3 +377,24 @@
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reg = <0>;
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};
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};
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/* BGX 2 */
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&bgx2 {
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status = "okay";
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/* SerDes 0, may differ from PCS Lane/LMAC */
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eth0: ethernet-mac@0 {
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compatible = "cavium,octeon-7890-bgx-port";
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reg = <0>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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sfp-slot = <&sfp0>;
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};
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/* SerDes 1, may differ from PCS Lane/LMAC */
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eth1: ethernet-mac@1 {
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compatible = "cavium,octeon-7890-bgx-port";
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reg = <1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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sfp-slot = <&sfp1>;
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};
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};
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