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Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog

Browse Source 
- octeontx_wdt: Add MIPS Octeon support (Stefan)
- watchdog: add amlogic watchdog support (Philippe)
- watchdog: add pulse support to gpio watchdog driver (Paul)
This commit is contained in:
Tom Rini 2022-07-22 20:48:28 -04:00
commit fd41c8f7a3
11 changed files with 292 additions and 38 deletions
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1
MAINTAINERS
View File

@ -161,6 +161,7 @@ F: drivers/spi/meson_spifc.c
F: drivers/pinctrl/meson/
F: drivers/power/domain/meson-gx-pwrc-vpu.c
F: drivers/video/meson/
F: drivers/watchdog/meson_gxbb_wdt.c
F: include/configs/meson64.h
F: include/configs/meson64_android.h
F: doc/board/amlogic/

11
arch/sandbox/dts/test.dts
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@ -850,10 +850,19 @@
};
};
gpio-wdt {
wdt-gpio-toggle {
gpios = <&gpio_a 7 0>;
compatible = "linux,wdt-gpio";
hw_margin_ms = <100>;
hw_algo = "toggle";
always-running;
};
wdt-gpio-level {
gpios = <&gpio_a 7 0>;
compatible = "linux,wdt-gpio";
hw_margin_ms = <100>;
hw_algo = "level";
always-running;
};

2
configs/octeon_ebb7304_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -90,4 +91,5 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_WDT=y
CONFIG_HEXDUMP=y

2
doc/board/amlogic/index.rst
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@ -73,6 +73,8 @@ This matrix concerns the actual source code version.
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* |
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
Boot Documentation
------------------

8
doc/device-tree-bindings/watchdog/gpio-wdt.txt
View File

@ -5,7 +5,12 @@ Describes a simple watchdog timer which is reset by toggling a gpio.
Required properties:
- compatible: Must be "linux,wdt-gpio".
- gpios: gpio to toggle when wdt driver reset method is called.
- gpios: From common gpio binding; gpio connection to WDT reset pin.
- hw_algo: The algorithm used by the driver. Should be one of the
following values:
- toggle: Toggle from high-to-low or low-to-high when resetting the watchdog.
- level: Maintain a constant high/low level, and trigger a short pulse when
resetting the watchdog. Active level is determined by the GPIO flags.
- always-running: Boolean property indicating that the watchdog cannot
be disabled. At present, U-Boot only supports this kind of GPIO
watchdog.
@ -15,5 +20,6 @@ Example:
gpio-wdt {
gpios = <&gpio0 1 0>;
compatible = "linux,wdt-gpio";
hw_algo = "toggle";
always-running;
};

16
drivers/watchdog/Kconfig
View File

@ -175,6 +175,13 @@ config WDT_MAX6370
help
Select this to enable max6370 watchdog timer.
config WDT_MESON_GXBB
bool "Amlogic watchdog timer support"
depends on WDT
help
Select this to enable Meson watchdog timer,
which can be found on some Amlogic platforms.
config WDT_MPC8xx
bool "MPC8xx watchdog timer support"
depends on WDT && MPC8xx
@ -213,14 +220,13 @@ config WDT_NPCM
It performs full SoC reset.
config WDT_OCTEONTX
bool "OcteonTX core watchdog support"
depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
bool "Octeon core watchdog support"
depends on WDT && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
default y
imply WATCHDOG
help
This enables OcteonTX watchdog driver, which can be
found on OcteonTX/TX2 chipsets and inline with driver model.
Only supports watchdog reset.
This enables the Octeon watchdog driver, which can be found on
various Octeon parts such as Octeon II/III and OcteonTX/TX2.
config WDT_OMAP3
bool "TI OMAP watchdog timer support"

1
drivers/watchdog/Makefile
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@ -27,6 +27,7 @@ obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o

40
drivers/watchdog/gpio_wdt.c
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@ -4,20 +4,38 @@
#include <dm/device_compat.h>
#include <wdt.h>
#include <asm/gpio.h>
#include <linux/delay.h>
enum {
HW_ALGO_TOGGLE,
HW_ALGO_LEVEL,
};
struct gpio_wdt_priv {
struct gpio_desc gpio;
bool always_running;
int state;
struct gpio_desc gpio;
unsigned int hw_algo;
bool always_running;
int state;
};
static int gpio_wdt_reset(struct udevice *dev)
{
struct gpio_wdt_priv *priv = dev_get_priv(dev);
priv->state = !priv->state;
return dm_gpio_set_value(&priv->gpio, priv->state);
switch (priv->hw_algo) {
case HW_ALGO_TOGGLE:
/* Toggle output pin */
priv->state = !priv->state;
dm_gpio_set_value(&priv->gpio, priv->state);
break;
case HW_ALGO_LEVEL:
/* Pulse */
dm_gpio_set_value(&priv->gpio, 1);
udelay(1);
dm_gpio_set_value(&priv->gpio, 0);
break;
}
return 0;
}
static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
@ -34,6 +52,16 @@ static int dm_probe(struct udevice *dev)
{
struct gpio_wdt_priv *priv = dev_get_priv(dev);
int ret;
const char *algo = dev_read_string(dev, "hw_algo");
if (!algo)
return -EINVAL;
if (!strcmp(algo, "toggle"))
priv->hw_algo = HW_ALGO_TOGGLE;
else if (!strcmp(algo, "level"))
priv->hw_algo = HW_ALGO_LEVEL;
else
return -EINVAL;
priv->always_running = dev_read_bool(dev, "always-running");
ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT);

136
drivers/watchdog/meson_gxbb_wdt.c Normal file
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@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022 BayLibre, SAS.
*/
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <reset.h>
#include <wdt.h>
#include <asm/io.h>
#include <linux/bitops.h>
#define GXBB_WDT_CTRL_REG 0x0
#define GXBB_WDT_TCNT_REG 0x8
#define GXBB_WDT_RSET_REG 0xc
#define GXBB_WDT_CTRL_SYS_RESET_NOW BIT(26)
#define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
#define GXBB_WDT_CTRL_CLK_EN BIT(24)
#define GXBB_WDT_CTRL_EE_RESET BIT(21)
#define GXBB_WDT_CTRL_EN BIT(18)
#define GXBB_WDT_CTRL_DIV_MASK GENMASK(17, 0)
#define GXBB_WDT_TCNT_SETUP_MASK GENMASK(15, 0)
struct amlogic_wdt_priv {
void __iomem *reg_base;
};
static int amlogic_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
if (timeout_ms > GXBB_WDT_TCNT_SETUP_MASK) {
dev_warn(dev, "%s: timeout_ms=%llu: maximum watchdog timeout exceeded\n",
__func__, timeout_ms);
timeout_ms = GXBB_WDT_TCNT_SETUP_MASK;
}
writel(timeout_ms, data->reg_base + GXBB_WDT_TCNT_REG);
return 0;
}
static int amlogic_wdt_stop(struct udevice *dev)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
data->reg_base + GXBB_WDT_CTRL_REG);
return 0;
}
static int amlogic_wdt_start(struct udevice *dev, u64 time_ms, ulong flags)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
data->reg_base + GXBB_WDT_CTRL_REG);
return amlogic_wdt_set_timeout(dev, time_ms);
}
static int amlogic_wdt_reset(struct udevice *dev)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
writel(0, data->reg_base + GXBB_WDT_RSET_REG);
return 0;
}
static int amlogic_wdt_expire_now(struct udevice *dev, ulong flags)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
writel(0, data->reg_base + GXBB_WDT_CTRL_SYS_RESET_NOW);
return 0;
}
static int amlogic_wdt_probe(struct udevice *dev)
{
struct amlogic_wdt_priv *data = dev_get_priv(dev);
int ret;
data->reg_base = dev_remap_addr(dev);
if (!data->reg_base)
return -EINVAL;
struct clk clk;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_enable(&clk);
if (ret) {
clk_free(&clk);
return ret;
}
/* Setup with 1ms timebase */
writel(((clk_get_rate(&clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) |
GXBB_WDT_CTRL_EE_RESET |
GXBB_WDT_CTRL_CLK_EN |
GXBB_WDT_CTRL_CLKDIV_EN,
data->reg_base + GXBB_WDT_CTRL_REG);
return 0;
}
static const struct wdt_ops amlogic_wdt_ops = {
.start = amlogic_wdt_start,
.reset = amlogic_wdt_reset,
.stop = amlogic_wdt_stop,
.expire_now = amlogic_wdt_expire_now,
};
static const struct udevice_id amlogic_wdt_ids[] = {
{ .compatible = "amlogic,meson-gxbb-wdt" },
{}
};
U_BOOT_DRIVER(amlogic_wdt) = {
.name = "amlogic_wdt",
.id = UCLASS_WDT,
.of_match = amlogic_wdt_ids,
.priv_auto = sizeof(struct amlogic_wdt_priv),
.probe = amlogic_wdt_probe,
.ops = &amlogic_wdt_ops,
.flags = DM_FLAG_PRE_RELOC,
};

67
drivers/watchdog/octeontx_wdt.c
View File

@ -15,16 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
#define CORE0_WDOG_OFFSET 0x40000
#define CORE0_POKE_OFFSET 0x50000
#define CORE0_POKE_OFFSET_MASK 0xfffffULL
#define WDOG_MODE GENMASK_ULL(1, 0)
#define WDOG_LEN GENMASK_ULL(19, 4)
#define WDOG_CNT GENMASK_ULL(43, 20)
struct octeontx_wdt_data {
u32 wdog_offset;
u32 poke_offset;
int timer_shift;
bool has_clk;
};
struct octeontx_wdt {
void __iomem *reg;
const struct octeontx_wdt_data *data;
struct clk clk;
};
@ -34,12 +40,16 @@ static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
u64 clk_rate, val;
u64 tout_wdog;
clk_rate = clk_get_rate(&priv->clk);
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
if (priv->data->has_clk) {
clk_rate = clk_get_rate(&priv->clk);
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
} else {
clk_rate = gd->bus_clk;
}
/* Watchdog counts in 1024 cycle steps */
tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
/* Watchdog counts in configured cycle steps */
tout_wdog = (clk_rate * timeout_ms / 1000) >> priv->data->timer_shift;
/*
* We can only specify the upper 16 bits of a 24 bit value.
@ -54,7 +64,7 @@ static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
val = FIELD_PREP(WDOG_MODE, 0x3) |
FIELD_PREP(WDOG_LEN, tout_wdog) |
FIELD_PREP(WDOG_CNT, tout_wdog << 8);
writeq(val, priv->reg + CORE0_WDOG_OFFSET);
writeq(val, priv->reg + priv->data->wdog_offset);
return 0;
}
@ -63,7 +73,7 @@ static int octeontx_wdt_stop(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
writeq(0, priv->reg + CORE0_WDOG_OFFSET);
writeq(0, priv->reg + priv->data->wdog_offset);
return 0;
}
@ -82,7 +92,7 @@ static int octeontx_wdt_reset(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
writeq(~0ULL, priv->reg + priv->data->poke_offset);
return 0;
}
@ -103,6 +113,10 @@ static int octeontx_wdt_probe(struct udevice *dev)
if (!priv->reg)
return -EINVAL;
priv->data = (void *)dev_get_driver_data(dev);
if (!priv->data)
return -EINVAL;
/*
* Save base register address in reg masking lower 20 bits
* as 0xa0000 appears when extracted from the DT
@ -110,13 +124,15 @@ static int octeontx_wdt_probe(struct udevice *dev)
priv->reg = (void __iomem *)(((u64)priv->reg &
~CORE0_POKE_OFFSET_MASK));
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
if (priv->data->has_clk) {
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
}
return 0;
}
@ -128,8 +144,23 @@ static const struct wdt_ops octeontx_wdt_ops = {
.expire_now = octeontx_wdt_expire_now,
};
static const struct octeontx_wdt_data octeontx_data = {
.wdog_offset = 0x40000,
.poke_offset = 0x50000,
.timer_shift = 10,
.has_clk = true,
};
static const struct octeontx_wdt_data octeon_data = {
.wdog_offset = 0x20000,
.poke_offset = 0x30000,
.timer_shift = 10,
.has_clk = false,
};
static const struct udevice_id octeontx_wdt_ids[] = {
{ .compatible = "arm,sbsa-gwdt" },
{ .compatible = "arm,sbsa-gwdt", .data = (ulong)&octeontx_data },
{ .compatible = "cavium,octeon-7890-ciu3", .data = (ulong)&octeon_data },
{}
};
@ -138,7 +169,7 @@ U_BOOT_DRIVER(wdt_octeontx) = {
.id = UCLASS_WDT,
.of_match = octeontx_wdt_ids,
.ops = &octeontx_wdt_ops,
.priv_auto = sizeof(struct octeontx_wdt),
.priv_auto = sizeof(struct octeontx_wdt),
.probe = octeontx_wdt_probe,
.remove = octeontx_wdt_remove,
.flags = DM_FLAG_OS_PREPARE,

46
test/dm/wdt.c
View File

@ -44,20 +44,20 @@ static int dm_test_wdt_base(struct unit_test_state *uts)
}
DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
static int dm_test_wdt_gpio(struct unit_test_state *uts)
static int dm_test_wdt_gpio_toggle(struct unit_test_state *uts)
{
/*
* The sandbox wdt gpio is "connected" to gpio bank a, offset
* 7. Use the sandbox back door to verify that the gpio-wdt
* driver behaves as expected.
* driver behaves as expected when using the 'toggle' algorithm.
*/
struct udevice *wdt, *gpio;
const u64 timeout = 42;
const int offset = 7;
int val;
ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
DM_DRIVER_GET(wdt_gpio), &wdt));
ut_assertok(uclass_get_device_by_name(UCLASS_WDT,
"wdt-gpio-toggle", &wdt));
ut_assertnonnull(wdt);
ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio));
@ -74,7 +74,39 @@ static int dm_test_wdt_gpio(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_wdt_gpio, UT_TESTF_SCAN_FDT);
DM_TEST(dm_test_wdt_gpio_toggle, UT_TESTF_SCAN_FDT);
static int dm_test_wdt_gpio_level(struct unit_test_state *uts)
{
/*
* The sandbox wdt gpio is "connected" to gpio bank a, offset
* 7. Use the sandbox back door to verify that the gpio-wdt
* driver behaves as expected when using the 'level' algorithm.
*/
struct udevice *wdt, *gpio;
const u64 timeout = 42;
const int offset = 7;
int val;
ut_assertok(uclass_get_device_by_name(UCLASS_WDT,
"wdt-gpio-level", &wdt));
ut_assertnonnull(wdt);
ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio));
ut_assertnonnull(gpio);
ut_assertok(wdt_start(wdt, timeout, 0));
val = sandbox_gpio_get_value(gpio, offset);
ut_assertok(wdt_reset(wdt));
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
ut_assertok(wdt_reset(wdt));
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
ut_asserteq(-ENOSYS, wdt_stop(wdt));
return 0;
}
DM_TEST(dm_test_wdt_gpio_level, UT_TESTF_SCAN_FDT);
static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts)
{
@ -86,8 +118,8 @@ static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts)
uint reset_count;
int val;
ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
DM_DRIVER_GET(wdt_gpio), &gpio_wdt));
ut_assertok(uclass_get_device_by_name(UCLASS_WDT,
"wdt-gpio-toggle", &gpio_wdt));
ut_assertnonnull(gpio_wdt);
ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
DM_DRIVER_GET(wdt_sandbox), &sandbox_wdt));