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2 Commits

Author SHA1 Message Date
Samuel Holland
a2615b3b16 riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-07-28 16:13:28 -05:00
Samuel Holland
5159250118 riscv: cpu: thead: Initialize extension CSRs 
Enable the T-HEAD ISA extensions, as these are required to use the cache
maintenance instructions. Enable the branch predictor and BTB to improve
performance. Some bits are only available on specific CPU models, so
provide Kconfig symbols for selecting the right model.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-07-28 16:13:28 -05:00