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2 Commits

Author SHA1 Message Date
Samuel Holland
a2615b3b16 riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-07-28 16:13:28 -05:00
Samuel Holland
ddbe65963d riscv: cpu: Add skeleton for T-HEAD CPUs 
This is a direct copy of the existing generic CPU code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-07-28 16:13:28 -05:00