12 Commits

Author SHA1 Message Date
Christian Marangi
cd06e60c44 mediatek: mt7988: move gpio-controller up and rename pinctrl to pio
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.

Update any DTS that reference the pinctrl to follow the new naming and
structure.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
8c2cb748ef pinctrl: mediatek: mt7988: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Weijie Gao
64cf3dd0ef arm: dts: mediatek: add support for all three GMACs for mt7988
This patch add all three GMACs nodes for mt7988. Each GMAC can be
configured to connect to different ethernet switches/PHYs.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23 12:11:49 -06:00
Weijie Gao
4064eb22e2 arm: dts: mediatek: add pcie support for mt7988
This patch adds PCIe support for mt7988

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23 12:11:49 -06:00
Christian Marangi
99c5fa184b clk: mediatek: mt7988: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:14:09 -06:00
Christian Marangi
ef4a648587 clk: mediatek: mt7988: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
8b75c2c479 clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
78507c3a9f clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.

Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
b76b75bfc6 clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Weijie Gao
3b51d5b76f arm: dts: mt7988-sd-rfb: add SD pin driving settings
Set SD pin driving to 4mA

Signed-off-by: Dong Huang <dong.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-03-01 16:35:52 -05:00
Frank Wunderlich
44bab4366f arm: mediatek: add usb support for MT7988
MT7988 has a t-phy and an x-phy controller. There is already a driver for
t-phy so we can add USB support for this phy type.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2023-08-17 16:39:20 -04:00
Weijie Gao
96b381e7bb arm: mediatek: add support for MediaTek MT7988 SoC
This patch adds basic support for MediaTek MT7988 SoC.
This includes files that will initialize the SoC after boot and
its device tree.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00