Add "cap-mmc-hw-reset" property to the eMMC DT node to perform the
eMMC device hardware reset.
Also, add "no-sd", "no-sdio" properties to eMMC DT node to skip
unwanted sd, sdio related commands during initialization for eMMC
device as this may lead to unnecessary register dump.
Signed-off-by: Paul Alvin <alvin.paulp@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b31554816a3378365143e9f5c266f6386af0a438.1727247785.git.michal.simek@amd.com
Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
