Judith Mendez <jm@ti.com> says:
This patch series enables ESM reset configuration in board_init_f
for am62x and am62px devices.
This is necessary in order for error events to reset the system.
This patches are tested using watchdog to reset the system via ESM.
Link: https://lore.kernel.org/r/20250129234403.574766-1-jm@ti.com
On AM62A and AM62P devices, it is possible to route Main ESM error
events to MCU ESM. MCU ESM high error output can trigger the reset
logic to reset the device. So, for these devices we have Main ESM and
MCU ESM nodes in the device tree. Add functions to probe these nodes
if CONFIG_ESM_K3 is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
The maximum frequency of the A53 CPU on the AM62P depends on the speed
grade of the SoC. This value is hardcoded in the DT for all AM62P
variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency.
Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
AM62P SoC has multiple speed grades. Add function to delete
non-relevant CPU frequency nodes, based on the information
retrieved from hardware registers. Fastest grade's maximum
frequency also depends on PMIC voltage, hence to simplify
implementation use the smaller value.
Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Read the max temperature for the SoC temperature grade from the hardware
and modify the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
AM62P SOC is available in multiple variants:
-CPU cores (Cortex-A) AM62Px1 (1 core),
AM62Px2 (2 cores), AM62Px4 (4 cores)
-With and without CAN-FD & Video-codec support
Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change it is possible to have a single
dts/dtb file handling the different variant at runtime.
Signed-off-by: Aparna Patra <a-patra@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
DDR intensive software applications can overwhelm the DSS's access to
the DDR because of their higher frequency DDR accesses. This can cause
flickering in display with certain applications running parallely if
the DSS traffic is being serviced through non-RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
The address we load TFA and OPTEE is configurable by the
CONFIG_K3_{ATF,OPTEE)_LOAD_ADDR, but the DT node reservations remain
static which can cause some confusion about where exactly these firmware
are exactly. Fix this by updating the reserved-memory{} nodes when the
loaded address does not match the address in DT.
Reported-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
