Add support for the R-Car S4 Starter Kit with R8A779F4 SoC support.
This implementation natively uses OF_UPSTREAM to pull in most recent
DT. The defconfig is derived from S4 Spider, with reduced UART baud
rate to 921600 Bdps. The DT alias to rswitch is removed as the alias
should point to rswitch ports, not to rswitch itself, see [1].
[1] https://lore.kernel.org/linux-arm-kernel/20250118111344.361617-5-marek.vasut+renesas@mailbox.org/
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add R-Car Gen4 APMU controller remoteproc driver capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
This requires slight adjustment to the SPL entry point code, as that
is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an
endless loop once it starts the rest of the SPL on Cortex-A76 core.
The endless loop now checks for content of APMU CRBARP registers and
tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the
Cortex-R52 core exits the endless loop and jumps to address started
in CRBARP[31:18] register in ARM mode, which is a trampoline code to
jump to the final entry point.
The trampoline code is in place to avoid limitation of CRBARP[31:18]
address field, which limits the core start address to memory addresses
aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000
aligned address and jumps to the final entry point, which can be at
an address with arbitrary alignment at instruction granularity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.
Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.
Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
This follows the example of RISC-V where <asm/global_data.h> includes
<asm/u-boot.h> directly as "gd" includes a reference to bd_info already
and so the first must include the second anyhow. We then remove
<asm/u-boot.h> from all of the places which include references to "gd"
an so have <asm/global_data.h> already.
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable OF_UPSTREAM to use upstream DT and add renesas/ prefix to the
DEFAULT_DEVICE_TREE and OF_LIST. And thereby directly build DTB from
dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/
directory.
The configuration update has been done using the following script:
```
sed -i '/^CONFIG_DEFAULT_DEVICE_TREE/ s@="@&renesas/@' `git grep -li renesas configs`
sed -i '/^CONFIG_OF_LIST/ s@r8a@renesas/&@g' `git grep -li renesas configs`
```
There are SoCs which are not included in this patch. The 32bit SoCs
require further infrastructure work. R8A779H0 is coming during the
next upstream DT synchronization cycle as it is not included in
current upstream DTs yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Adam Ford <aford173@gmail.com> # Beacon boards
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Marek Vasut <marek.vasut+renesas@mailbox.org> says:
Rename R-Mobile to Renesas all over the place because the chips are
made by Renesas, while only a subset of them is from the R-Mobile line.
Fix up remains of rename from rmobile to renesas,
namely file paths and remaining RMOBILE strings.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Rename arch-rmobile to arch-renesas and mach-rmobile to mach-renesas
because all the chips are made by Renesas, while only a subset of
them is from the R-Mobile line.
Use the following command to perform the rename, with manual move of
the directories using git mv and manual fix up to arch/arm/Makefile:
"
$ git grep -l '\<\(arch\|mach\)-rmobile\>' | \
xargs -I {} sed -i 's@\<\(arch\|mach\)-rmobile\>@\1-renesas@g' {}
$ sed -i 's@rmobile@renesas@' board/*/*/Kconfig
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
