5 Commits

Author SHA1 Message Date
Rasmus Villemoes
52ec7b7c89 treewide: drop redundant "type string" for SYS_SOC and friends
The Kconfig symbols SYS_ARCH, SYS_CPU, SYS_SOC, SYS_VENDOR and
SYS_BOARD are defined in arch/Kconfig as having type string, and most
board files simply amend those definition with suitable

  default "foo"

or

  default "foo" if BAR

stanzas. But some also include a redundant repetition of the type.

Homogenize the code base by removing those lines.

Generated by

  find arch/*/ board -name Kconfig | xargs perl -i -g -pe 's/(config SYS_(ARCH|CPU|SOC|VENDOR|BOARD)\n)\s*string\n/\1/gs'

with the trailing slash in arch/*/ ensuring that arch/Kconfig itself
is not found.

This does not change boards which add a prompt string, e.g.

  string "Board name"

because I think those change the semantics of the symbol into being
user-settable.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-09-10 13:14:59 -06:00
Stefan Roese
ec85347102 mips: octeon: Add Octeon III NIC23 board support
This patch adds the basic support for the PCIe target board equipped
with the Octeon III CN2350 SoC.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:22:55 +02:00
Stefan Roese
99f492b75f mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT
Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on
MIPS Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:03:25 +02:00
Stefan Roese
5fef24c912 mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.

Supported devices:
- UART
- reset
- CFI parallel NOR flash

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00
Aaron Williams
0dc4ab9c43 mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00