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3 Commits

Author SHA1 Message Date
Simon Glass
dac3ce976a board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
 2024-10-11 11:44:48 -06:00
Michal Simek
80fdef12b2 xilinx: Introduce board_late_init_xilinx() 
This function should keep common shared late configurations for Xilinx
SoCs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2020-04-27 13:57:17 +02:00
Ezequiel Garcia
c66f5620e6 arm: zynq: Add support for Bitmain Antminer S9 control board 
This is control board on Bitmain Antminer S9.
There are 3 board variables with 256MB, 512MB and 1024MB DDR.
DDR memory is automatically detected with using get_with using
get_ram_size().

Bitmain is using 16MB space for FPGA which is handled via
reserved-memory. Also U-Boot is allocating 16B for storing bootcounts.
Watchdog is started but never service in U-Boot.

SPL MMC is working. SPL NAND is not working because it is not supported
as of now.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-05-31 13:50:39 +02:00