Currently, booting via bootstd fails because the kernel cannot be retrieved.
The reason for this is the lack of 'kernel_addr_r'.
Pass 'kernel_addr_r' to fix booting via bootstd.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Improve "mmcautodetect=yes" boot mode autodetection to able to use it
if CONFIG_ENV_IS_NOWHERE=y is used for i.MX9 SoCs and i.MX93 EVK board.
If both CONFIG_ENV_IS_IN_MMC=y and CONFIG_ENV_IS_NOWHERE=y are in the
defconfig, CONFIG_ENV_IS_IN_MMC=y will be overiden default
CONFIG_ENV_IS_NOWHERE settings.
Goal is in this patch to able to use the boot mode autodetection
if defconfig use only CONFIG_ENV_IS_NOWHERE=y option
(without CONFIG_ENV_IS_IN_MMC) for any i.MX9 SoC.
Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu>
Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from this board vendor directory and when needed
add missing include files directly.
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The following information printed on every boot is not very
helpful for the users:
SOC: 0xa0009300
LC: 0x40040
Move them to debug() level.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Mathieu Othacehe <othacehe@gnu.org>
Put imx9_probe_mu declaration in a new mu.h header file.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Add a common board_interface_eth_init() called by the DWC MAC driver to
setup the MAC <-> PHY interface according to the PHY mode obtained from
DT.
Remove the board-side configuration in the i.MX93 EVK files.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
1. Convert all linker symbols to char[] type so that we can get the
corresponding address by calling array name 'var' or its address
'&var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
standard header file to declare them.
[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL
Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are a few entries where minor mistakes mean that we don't match up
with obviously expected files, correct those.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Update DDR timing file generated by DDR Config Tool
1. Dynamic refresh rate is set by default
2. The 3rd freq will be 625MTS based on power and performance better than 100MTS.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_FEC_MXC defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_DWC_ETH_QOS defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
The PCA9450 reset configuration can now be performed by the PCA9450 PMIC
driver itself, remove the hard-coded variant from board code and let the
PMIC driver perform this task using one-liner:
```
$ sed -i '/set WDOG_B_CFG to cold reset/,+2 d' $(git grep -l PCA9450_RESET_CTRL.*0xA1 board/)
```
Venice and i.MX93 EVK required slight manual fix up.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
