With commit 22ce56a3ebdb ("ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc()
to solve 'calculations restricted to 32 bits' issue") we need to provide the
detected RAM size in the device tree node prio to K3 DDRSS driver probe.
This is done by calling fdt_fixup_memory_banks() in do_board_detect().
After probing, call into k3-ddrss driver to fixup device tree and resize
the available amount of DDR if ECC is enabled.
A third fixup is required from A53 SPL to take the fixup
as done from R5 SPL and apply it to DT passed to A53 U-boot,
which in turn passes this to the OS.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code
optional for PHYTEC K3 boards. This allows better control over which
boards receive DDR timing patches, rather than compiling the code for
all boards with K3_DDRSS enabled.
Also enable the feature by default for PHYCORE_AM62X_R5.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Daniel Schultz <d.schultz@phytec.de> says:
This patch stack extends the phyCORE-AM62x/AM64x U-Boot by following boot
sources:
- Load U-Boot with USB DFU
- Load a Linux and initramfs from OSPI/QSPI NOR flash
- Load a Linux and rootfs from Network
Moreover, it adds required changes to the environment to boot an A/B
system with RAUC and includes some minor fixes.
Include the boot logic to boot via Network or from a OSPI/QSPI
NOR flash. Moreover, set all required variables to both boot
methods to the environment.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
By moving the earlycon definition into a dedicated variable, it's
easier to change these values in case the kernel should print on
a different serial interface.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
There is no need to reread the EEPROM multiple times in different stages
to detect the RAM size. We can do this once at an early stage and let
higher stages decode memory nodes using fdtdec.
Make sure to pass fixup memory nodes before passing to u-boot stage.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Pull in ti/k3_dfu.env for dfu_alt_info_ram in SPL stage.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Use content of EEPROM to detect the actual RAM size and adjust
DDR timings, size and banks accordingly.
Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Introduce fdt_apply_ddrss_timings_patch() to allow board code to
override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Environment handling code can be reused across all our K3 based SoMs.
Instead of adding the same code for every new SoM, move it to a common
board.c file.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Daniel Schultz <d.schultz@phytec.de> says:
This patch series extends PHYTEC's SOM detection by minor
fixes, a generic helper function and a new valid flag.
Moreover, it adds a module to provide access to the SOM
detection for our TI AM6 products.
Add all functions to read each SOM option from the EEPROM
image and detect whether it's the correct product for this
image.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The phycore-am62x can be migrated to OF_UPSTREAM.
Drop redundant device tree files, update MAINTAINERS and
defconfig's DEFAULT_DEVICE_TREE for ti vendor prefix accordingly.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Select environment location based on the device we boot from.
Also, introduce a "boot" variable that represents the current boot
device and can be used by scripts.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Clean up all configuration files to adhere to yamllint rules.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[trini: Update more yaml files added since this was posted]
Signed-off-by: Tom Rini <trini@konsulko.com>
Suggested-by: Nishanth Menon <nm@ti.com>
