Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fix up
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Prasanth Babu Mantena <p-mantena@ti.com> says:
The channel allocation and deallocation for dma copy was happening on every
dma transfer. This is a overhead for transactions like NAND, which does
page reads recursively for complete data.
So, moving the dma allocation to probe and implement corresponding
remove function and cleanup dma device while exiting from spl.
Enable SPL_DM_DEVICE_REMOVE, for device removal capability in SPL.
Link: https://lore.kernel.org/r/20241009145703.1970034-1-p-mantena@ti.com
Make the raw-mode options depend on SPL_SYS_MMCSD_RAW_MODE in a more
direct way. This makes it easier to understand the options with
'make menuconfig'.
There are three different ways of specifying the offset:
- sector offset
- partition number
- partition type
So make these a choice, so it is more obvious what is going on.
Update existing boards to enable SPL_SYS_MMCSD_RAW_MODE where needed.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
All ARCH_K3 platforms need about of 2MB of malloc space post
reallocation. Since, this space is allocated from SDRAM, provide a
generous 2MB space by default.
Platforms requiring more than 2MB can override in defconfig as needed.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
On AM62x SK we can see a boot failure with signature "alloc space
exhausted", so fix by increasing size of SPL_STACK_R_MALLOC_SIMPLE_LEN.
Fixes: 128f81290b ("arm: dts: k3: binman: am625: add support for signing TIFSSTUB Images")
Signed-off-by: Judith Mendez <jm@ti.com>
Tested-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that select/imply one type of flash, but did not do the same, also do
this for "MTD". Make boards which hadn't been enabling MTD already but
need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it
wasn't previously enabled but was now being implied.
Signed-off-by: Tom Rini <trini@konsulko.com>
All K3 boards now are secure by default, instead of setting this in each
defconfig, make it implied by the ARCH config.
The only exception is IOT2050, which I do not believe will have any
problems with being a TI_SECURE_DEVICE, but for now turn it off to keep
its config the same.
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Enable the CONFIG_TI_SECURE_DEVICE by default
Non-HS devices will continue to boot due to runtime device type detection.
TI's security enforcing SoCs will authenticate each binary it loads by
comparing it's signature with keys etched into the SoC during the boot
up process. The am62x family of SoCs by default will have some level of
security enforcement checking. To keep things as simple as possible,
enable the CONFIG_TI_SECURE_DEVICE options by default so all levels of
secure SoCs will work out of the box
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.
This means we will need to move the stack & heap from OCSRAM to HSM RAM
and reduce the size of BSS and the SPL to allow it to fit properly.
To protect us from overflowing our ~256k of HSM SRAM, add limits and
check during the wakeup SPL build.
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
In f422c4bec the configuration option to support s28hs512t SPI flashes
was changed from CONFIG_SPI_FLASH_S28HS512T to CONFIG_SPI_FLASH_S28HX_T
to support the wider family. Follow this change in the AM62x EVM
configurations.
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Add am62x_evm_r5_defconfig for OSPI Flash support in R5 SPL
and am62x_evm_a53_defconfig for A53 SPL and U-Boot
support.
These configs enable OSPI Flash boot functionality in the board as well
as the usage of OSPI Flash from U-Boot.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is
needed to calculate the size of DDR that is available.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for
A53 SPL and U-Boot support.
To keep the changes to minimum. Only UART And SD boot related configs
are included. This should serve as good starting point for new board
bringup with AM62x.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[trini: Migrate a number of CONFIG symbols, have re-tested]
Tested-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
