11 Commits

Author SHA1 Message Date
Tom Rini
d892702080 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-10-08 09:28:10 -06:00
Sam Edwards
bc7cb4b67a configs: rk3588-turing-rk1: disable SPI flash by default
While the Turing RK1 board has a pad on the PCB for SPI flash, it is
not populated at the factory: supporting SPI flash boot is a user
modification, not an out-of-the-box feature. The defconfig for this
board should therefore not be enabling the SPI flash image nor SPI
support in the SPL, as it causes confusion among downstream users as to
whether the SPI image needs to be distributed.

Fixes: 153ac950a599 ("board: rockchip: Add the Turing RK1 SoM")
Suggested-by: Florian Klink <flokli@flokli.de>
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Acked-by: Joshua Riek <jjriek@verizon.net>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-05-07 15:56:10 +08:00
Jonas Karlman
d4fd24ffe4 rockchip: rk3588: Migrate to OF_UPSTREAM
Migrate RK3588 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is not migrated to use OF_UPSTREAM:
- generic-rk3588: Generic target only meant for U-Boot use
- toybrick-rk3588: Merged in v6.9-rc1

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-05-07 15:56:10 +08:00
Quentin Schulz
9331744a4c rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.

Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.

Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.

The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.

Co-developed-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26 15:47:05 +08:00
Jonas Karlman
4c1722ffd1 rockchip: rk3588-turing-rk1: Use dwc3-generic driver
RK35xx boards are expected to use the dwc3-generic driver and not the
xhci-dwc3 driver.

Remove the USB_XHCI_DWC3 option to ensure that the dwc3-generic driver
is used.

Fixes: 153ac950a599 ("board: rockchip: Add the Turing RK1 SoM")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26 15:47:05 +08:00
Jonas Karlman
a74243c631 rockchip: rk3588: Drop REGULATOR_PWM Kconfig option
RK3588 boards do not have any pwm-regulator compatible nodes in DT, drop
the superfluous REGULATOR_PWM Kconfig options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26 15:47:04 +08:00
Tom Rini
18e791c404 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-22 17:40:37 -06:00
Jonas Karlman
b0cadb35da rockchip: Use common bss and stack addresses on RK3588
Currently the following memory layout is typically used on RK3588:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[ 3.5M,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,   6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[   5M,   6M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[  10M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,  12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[11.5M,  12M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[  64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)

SPL can safely load U-Boot proper + FDT to [10M, 11.5M) with this layout.

However, on ROCK 5A the SPL stacks is overlapping:
[   -X,  16M) - SPL pre-reloc stack (SPL_STACK)
[15.5M,  16M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,  16M) - SPL reloc stack (SPL_STACK_R_ADDR)
[  15M,  16M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)

Because bind and probe udevice instanses is allocated on the pre-reloc
malloc heap, there is going to be an overlap when reloc malloc heap
reaches close to 512 KiB of usage.

Migrate to use common bss, stack and malloc heap size and addresses to
mitigate these limitations and allow for a larger U-Boot proper size.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for new boards defconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2024-03-14 15:30:16 +08:00
Tom Rini
19f6576007 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-01 09:10:04 -05:00
Jonas Karlman
8ef97f8138 rockchip: rk3588: Enable eMMC HS200 mode
Writing to eMMC using HS200 mode work more reliably then other modes on
RK3588 boards.

Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Weizhao Ouyang <o451686892@gmail.com>
2024-02-05 15:00:32 +08:00
Joshua Riek
153ac950a5 board: rockchip: Add the Turing RK1 SoM
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.

Specifications:

    Rockchip RK3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    8/16/32GB memory LPDDR4x
    Mali G610MC4 GPU
    32GB eMMC HS400
    2x USB 2.0, 2x USB 3.0
    2x MIPI CSI 4x lanes
    1x MIPI-DSI DPHY 2x lanes
    PCIe 2.0 x1, PCIe 3.0 x4
    1x HDMI 2.1 output, 1x DP 1.4 output
    Gigabit Ethernet
    Size: 69.6mm x 45mm (260-pin SO-DIMM connector)

Kernel commit:
2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support")

Signed-off-by: Joshua Riek <jjriek@verizon.net>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00